
Rev.3.00
Aug 06, 2004
page 133 of 136
REJ03B0043-0300Z
4554 Group
BASIC TIMING DIAGRAM
VOLTAGE DROP DETECTION CIRCUIT CHARACTERISTICS
(Ta = –20 °C to 85 °C, unless otherwise noted)
Test conditions
Ta = 25 °C
at power down
VDD = 5 V
(Note 2)
VDD = 3 V
VDD
→ (VRST–0.1 V) (Note 3)
Parameter
Detection voltage (Note 1)
Operation current
Detection time
Symbol
VRST
IRST
TRST
Limits
Unit
Min.
1.4
1.1
Typ.
1.5
50
30
0.2
Max.
1.6
1.9
100
60
1.2
V
A
ms
Notes 1: The detected voltage (VRST) is defined as the voltage when reset occurs when the supply voltage (VDD) is falling.
2: After the SVDE instruction is executed, the voltage drop detectin circuit is valid at power down mode.
3: The detection time (TRST) is defined as the time until reset occurs when the supply voltage (VDD) is falling to [VRST–0.1 V].
STCK
Parameter
Pin (signal) name
Machine cycle
MiMi+1
D0–D9
System clock
Port D output
Port D input
Ports P0, P1 output
Ports P0, P1, P2, P3
input
D0–D7
INT0, INT1
Interrupt input
P00–P03
P10–P13
P00–P03
P10–P13
P20–P23
P30–P33