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參數(shù)資料
| 型號： | M34519M8-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO42 |
| 封裝： | 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-42 |
| 文件頁數(shù)： | 94/138頁 |
| 文件大小： | 1146K |
| 代理商： | M34519M8-XXXFP |
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4519 Group
Rev.3.01
2005.06.15
page 57 of 160
REJ03B0007-0301
Table 16 Processing sequence of data transfer from master to slave
1-byte data is serially transferred on this process. Subsequently, data
can be transferred continuously by repeating the process from *.
When an external clock is selected as a synchronous clock, the
clock is not controlled internally. Control the clock externally be-
cause serial transfer is performed as long as clock is externally
input. (Unlike an internal clock, an external clock is not stopped
when serial transfer is completed.) However, the SIOF flag is set to
“1” when the clock is counted 8 times after executing the SST in-
struction. Be sure to set the initial level of the external clock to “H.”
Master (transmission)
[Initial setting]
Setting the serial I/O mode register J1 and inter-
rupt control register V2 shown in Figure 44.
TJ1A and TV2A instructions
Setting the port received the reception enable
signal (SRDY) to the input mode.
(Port D3 is used in this example)
SD instruction
* [Transmission enable state]
Storing transmission data to serial I/O register SI.
TSIAB instruction
[Transmission]
Check port D3 is “L” level.
SZD instruction
Serial transfer starts.
SST instruction
Check transmission completes.
SNZSI instruction
Wait (timing when continuously transferring)
Slave (reception)
[Initial setting]
Setting serial I/O mode register J1, and interrupt control register V2 shown in
Figure 44.
TJ1A and TV2A instructions
Setting the port transmitted the reception enable signal (SRDY) and outputting
“H” level (reception impossible).
(Port D3 is used in this example)
SD instruction
*[Reception enable state]
The SIOF flag is cleared to “0.”
SST instruction
“L” level (reception possible) is output from port D3.
RD instruction
[Reception]
Check reception completes.
SNZSI instruction
“H” level is output from port D3.
SD instruction
[Data processing]
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