參數(shù)資料
型號(hào)： M34513E4SP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
中文描述： 單芯片4位微機(jī)的CMOS
文件頁(yè)數(shù)： 22/106頁(yè)
文件大?。?/td> 1304K
代理商： M34513E4SP
22
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
(6) Interrupt control registers
Interrupt control register V1
Interrupt enable bits of external 0, external 1, timer 1 and timer 2
are assigned to register V1. Set the contents of this register
through register A with the TV1A instruction. The TAV1 instruction
can be used to transfer the contents of register V1 to register A.
Interrupt control register V2
Interrupt enable bits of timer 3, timer 4, A-D and serial I/O are as-
signed to register V2. Set the contents of this register through
register A with the TV2A instruction. The TAV2 instruction can be
used to transfer the contents of register V2 to register A.
Table 6 Interrupt control registers
V1
3
V1
2
V1
1
V1
0
V2
3
V2
2
V2
1
V2
0
Serial I/O interrupt enable bit
A-D interrupt enable bit
Timer 4 interrupt enable bit
Timer 3 interrupt enable bit
Interrupt control register V1
Timer 2 interrupt enable bit
Timer 1 interrupt enable bit
External 1 interrupt enable bit
External 0 interrupt enable bit
Note: “R” represents read enabled, and “W” represents write enabled.
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid)
Interrupt disabled (SNZ1 instruction is valid)
Interrupt enabled (SNZ1 instruction is invalid)
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
Interrupt disabled (SNZSI instruction is valid)
Interrupt enabled (SNZSI instruction is invalid)
Interrupt disabled (SNZAD instruction is valid)
Interrupt enabled (SNZAD instruction is invalid)
Interrupt disabled (SNZT4 instruction is valid)
Interrupt enabled (SNZT4 instruction is invalid)
Interrupt disabled (SNZT3 instruction is valid)
Interrupt enabled (SNZT3 instruction is invalid)
0
1
0
1
0
1
0
1
R/W
at RAM back-up : 0000
2
at reset : 0000
2
Interrupt control register V2
R/W
at RAM back-up : 0000
2
at reset : 0000
2
0
1
0
1
0
1
0
1
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