- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄69010 > M34501E4FP 4-BIT, OTPROM, MICROCONTROLLER, PDSO20 PDF資料下載
參數(shù)資料
| 型號(hào)： | M34501E4FP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, OTPROM, MICROCONTROLLER, PDSO20 |
| 封裝： | 5.30 X 12.60 MM, 1.27 MM PITCH, PLASTIC, SOP-20 |
| 文件頁(yè)數(shù)： | 34/116頁(yè) |
| 文件大?。?/td> | 859K |
| 代理商： | M34501E4FP |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)當(dāng)前第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)
Rev.3.01
2005.02.07
page 24 of 112
REJ03B0104-0301
4501 Group
(3) Notes on interrupts
Note [1] on bit 3 of register I1
When the input of the INT pin is controlled with the bit 3 of regis-
ter I1 in software, be careful about the following notes.
Depending on the input state of the P13/INT pin, the external 0 in-
terrupt request flag (EXF0) may be set when the bit 3 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 18)
and then, change the bit 3 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to
“0” after executing at least one instruction (refer to Figure 18).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ0 instruction (refer to Figure 18).
LA
4
; (02)
TV1A
; The SNZ0 instruction is valid ...........
LA
8
; (12)
TI1A
; Control of INT pin input is changed
NOP
...........................................................
SNZ0
; The SNZ0 instruction is executed
(EXF0 flag cleared)
NOP
...........................................................
: these bits are not used here.
Fig. 18 External 0 interrupt program example-1
Note [2] on bit 3 of register I1
When the bit 3 of register I1 is cleared to “0”, the RAM back-up
mode is selected and the input of INT pin is disabled, be careful
about the following notes.
When the key-on wakeup function of port P13 is not used (regis-
ter K13 = “0”), clear bits 2 and 3 of register I1 before system
enters to the RAM back-up mode. (refer to Figure 19).
LA
0
; (002)
TI1A
; Input of INT disabled ........................
DI
EPOF
POF
; RAM back-up
: these bits are not used here.
Fig. 19 External 0 interrupt program example-2
Note [3] on bit 2 of register I1
When the interrupt valid waveform of the P13/INT pin is changed
with the bit 2 of register I1 in software, be careful about the fol-
lowing notes.
Depending on the input state of the P13/INT pin, the external 0 in-
terrupt request flag (EXF0) may be set when the bit 2 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 20)
and then, change the bit 2 of register I1 is changed.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to
“0” after executing at least one instruction (refer to Figure 20).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ0 instruction (refer to Figure 20).
LA
4
; (02)
TV1A
; The SNZ0 instruction is valid ...........
LA
12
; (12)
TI1A
; Interrupt valid waveform is changed
NOP
...........................................................
SNZ0
; The SNZ0 instruction is executed
(EXF0 flag cleared)
NOP
...........................................................
: these bits are not used here.
Fig. 20 External 0 interrupt program example-3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M34502M2-XXXFP | 4-BIT, MROM, MICROCONTROLLER, PDSO24 |
| M34502M4-XXXFP | 4-BIT, MROM, MICROCONTROLLER, PDSO24 |
| M34506M4-XXXFP | 4-BIT, MROM, MICROCONTROLLER, PDSO20 |
| M34506E4FP | 4-BIT, OTPROM, MICROCONTROLLER, PDSO20 |
| M34508G4HFP | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M34501M2 | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34501M2-XXXFP | 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34501M4 | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34501M4-XXXFP | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34502E4 | 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。