參數(shù)資料
型號: M34501E4FP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, OTPROM, MICROCONTROLLER, PDSO20
封裝: 5.30 X 12.60 MM, 1.27 MM PITCH, PLASTIC, SOP-20
文件頁數(shù): 62/118頁
文件大?。?/td> 952K
代理商: M34501E4FP
Rev.3.01
2005.02.07
page 46 of 112
REJ03B0104-0301
4501 Group
CLOCK CONTROL
The clock control circuit consists of the following circuits.
On-chip oscillator (internal oscillator)
Ceramic resonator
RC oscillation circuit
Multi-plexer (clock selection circuit)
Frequency divider
Internal clock generating circuit
Fig. 42 Clock control circuit structure
The system clock and the instruction clock are generated as the
source clock for operation by these circuits.
Figure 42 shows the structure of the clock control circuit.
The 4501 Group operates by the on-chip oscillator clock (f(RING))
which is the internal oscillator after system is released from reset.
Also, the ceramic resonator or the RC oscillation can be used for
the source oscillation (f(XIN)) of the 4501 Group. The CMCK in-
struction or CRCK instruction is executed to select the ceramic
resonator or RC oscillator, respectively.
MR3, MR2
00
01
10
11
Q S
QR
Q S
R
CRCK instruction
Q S
R
CMCK
instruction
Q S
R
RESET pin
XOUT
XIN
Key-on wakeup signal
Instruction clock
Counter
Wait time (Note 2)
control circuit
Program
start signal
RC oscillation circuit
Division circuit
divided by 8
divided by 4
divided by 2
Internal clock
generation circuit
(divided by 3)
Notes 1: System operates by the on-chip oscillator clock (f(RING)) until the CMCK or CRCK instruction
is executed after system is released from reset.
2: The wait time control circuit is used to generate the time required to stabilize the f(XIN) oscillation.
After the certain oscillation stabilizing wait time elapses, the program start signal is output.
This circuit operates when system is released from reset or returned from RAM back-up.
System clock
On-chip oscillator
(internal oscillator)
(Note 1)
Multiplexer
Ceramic resonator
circuit
POF or
EPOF instruction + POF2
instruction
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