參數(shù)資料
型號(hào)： M34283G2GP
元件分類(lèi)： 微控制器/微處理器
英文描述： 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20
封裝： 4.40 X 6.50 MM, 0.65 MM PITCH, PLASTIC, LSSOP-20
文件頁(yè)數(shù)： 2/41頁(yè)
文件大?。?/td> 441K
代理商： M34283G2GP
Rev.1.01
Mar 20, 2006
page 8 of 62
REJ03B0109-0101
4283 Group
Fig. 5 Stack registers (SKs) structure
Fig. 6 Example of operation at subroutine call
(5) Most significant ROM code reference enable flag (URS)
URS flag controls whether to refer to the contents of the most
significant 1 bit (bit 8) of ROM code when executing the TABP
p instruction. If URS flag is “0,” the contents of the most
significant 1 bit of ROM code is not referred even when
executing the TABP p instruction. However, if URS flag is “1,”
the contents of the most significant 1 bit of ROM code is set to
flag CY when executing the TABP p instruction (Figure 4).
URS flag is “0” after system is released from reset and returned
from RAM back-up mode. It can be set to “1” with the URSC
instruction, but cannot be cleared to “0.”
(6) Stack registers (SKs) and stack pointer (SP)
Stack registers (SKs) are used to temporarily store the contents
of program counter (PC) just before branching until returning
to the original routine when;
performing a subroutine call, or
executing the table reference instruction (TABP p).
Stack registers (SKs) are four identical registers, so that
subroutines can be nested up to 4 levels. However, one of
stack registers is used when executing a table reference
instruction. Accordingly, be careful not to over the stack. The
contents of registers SKs are destroyed when 4 levels are
exceeded.
The register SK nesting level is pointed automatically by 2-bit
stack pointer (SP).
Figure 5 shows the stack registers (SKs) structure.
Figure 6 shows the example of operation at subroutine call.
(7) Skip flag
Skip flag controls skip decision for the conditional skip
instructions and continuous described skip instructions.
Note : The 4283 Group just invalidates the next instruction
when a skip is performed. The contents of program
counter is not increased by 2. Accordingly, the number
of cycles does not change even if skip is not performed.
However, the cycle count becomes “1” if the TABP p,
RT, or RTS instruction is skipped.
SK0
SK1
SK2
SK3
(SP) = 0
(SP) = 1
(SP) = 2
(SP) = 3
Program counter (PC)
Executing RT
instruction
Executing BM
instruction
Stack pointer (SP) points “3” at reset or
returning from RAM back-up mode. It points “0”
by executing the first BM instruction, and the
contents of program counter is stored in SK0.
When the BM instruction is executed after four
stack registers are used ((SP) = 3), (SP) = 0
and the contents of SK0 is destroyed.
Returning to the BM instruction execution
address with the RT instruction, and the BM
instruction is equivalent to the NOP instruction.
(SP)
← 0
(SK0)
← 000116
(PC)
← SUB1
Main program
000216 NOP
Address
000016 NOP
000116 BM SUB1
Subroutine
SUB1 :
NOP
RT
(PC)
← (SK0)
(SP)
← 3
Note:
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M34283G2GP#U1 制造商:Renesas Electronics Corporation 功能描述:MICROCONTROLLER
M34283G2-XXXGP 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
M34286 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
M34286G2GP 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
M34286G2GP#U0 功能描述:MCU 1.8/3.6V 2KB ROM 20-LSSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:720/4500 標(biāo)準(zhǔn)包裝:38 系列:Encore!® XP® 核心處理器:eZ8 芯體尺寸:8-位 速度:5MHz 連通性:IrDA，UART/USART 外圍設(shè)備:欠壓檢測(cè)/復(fù)位，LED，POR，PWM，WDT 輸入/輸出數(shù):16 程序存儲(chǔ)器容量:4KB（4K x 8） 程序存儲(chǔ)器類(lèi)型:閃存 EEPROM 大小:- RAM 容量:1K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 105°C 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 包裝:管件 其它名稱(chēng):269-4116Z8F0413SH005EG-ND
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