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參數(shù)資料
| 型號： | M34280M1-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | 0.300 INCH, 1.27 MM PITCH, PLASTIC, SOP-20 |
| 文件頁數(shù)： | 39/48頁 |
| 文件大小： | 605K |
| 代理商： | M34280M1-XXXFP |
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Interrupt
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
43
Interrupt Enable Flag (I flag)
The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this
flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set
to “0” after reset.
Interrupt Request Bit
The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is
accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The
interrupt request bit can also be set to "0" by software. (Do not set this bit to "1").
Table 1.10.4. Interrupt levels enabled according
to the contents of the IPL
Table 1.10.3. Settings of interrupt priority
levels
Interrupt priority
level select bit
Interrupt priority
level
Priority
order
0
1
0
1
0
1
0
1
0
1
0
1
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Low
High
b2 b1 b0
Enabled interrupt priority levels
0
1
0
1
0
1
0
1
0
1
0
1
Interrupt levels 1 and above are enabled
Interrupt levels 2 and above are enabled
Interrupt levels 3 and above are enabled
Interrupt levels 4 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 6 and above are enabled
Interrupt levels 7 and above are enabled
All maskable interrupts are disabled
IPL2 IPL1 IPL0
IPL
Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)
Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits
of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared
with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL.
Therefore, setting the interrupt priority level to “0” disables the interrupt.
Table 1.10.3 shows the settings of interrupt priority levels and Table 1.10.4 shows the interrupt levels
enabled, according to the contents of the IPL.
The following are conditions under which an interrupt is accepted:
interrupt enable flag (I flag) = 1
interrupt request bit = 1
interrupt priority level > IPL
The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are
independent, and they are not affected by one another.
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PDF描述 |
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| M34280M1-XXXGP | 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20 |
| M34280E1GP | 4-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDSO20 |
| M34501M2-XXXFP | 4-BIT, MROM, 4.4 MHz, MICROCONTROLLER, PDSO20 |
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| M34501M2-XXXFP | 4-BIT, MROM, MICROCONTROLLER, PDSO20 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M34280M1-XXXGP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS |
| M3428-100 | 制造商:MANHATTEN 功能描述:24AWG COMPUTER CABLE |
| M34282 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34282E2 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34282E2GP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
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