Mitsubishi Microcomputers
43
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
2001-5-14 Rev.1.0
32170 Group, 32174 Group
CPU Instruction Set
The M32R employs a RISC architecture, supporting a total
of 83 discrete instructions.
(1) Load/store instructions
Perform data transfer between memory and registers.
LD
LDB
LDUB
LDH
LDUH
LOCK
ST
STB
STH
UNLOCK
Load
Load byte
Load unsigned byte
Load halfword
Load unsigned halfword
Load locked
Store
Store byte
Store halfword
Store unlocked
(2) Transfer instructions
Perform register to register transfer or register to immediate
transfer
.
LD24
Load 24-bit immediate
LDI
Load immediate
MV
Move register
MVFC
Move from control register
MVTC
Move to control register
SETH
Set high-order 16-bit
(3) Branch instructions
Used to change the program flow.
BC
BEQ
Branch on equal
BEQZ
Branch on equal zero
BGEZ
Branch on greater than or equal zero
BGTZ
Branch on greater than zero
BL
Branch and link
BLEZ
Branch on less than or equal zero
BLTZ
Branch on less than zero
BNC
Branch on not C-bit
BNE
Branch on not equal
BNEZ
Branch on not equal zero
BRA
Branch
JL
Jump and link
JMP
Jump
NOP
No operation
(4) Arithmetic/logic instructions
Perform comparison, arithmetic/logic operation, multiplica-
tion/division, or shift between registers.
Comparison
Branch on C-bit
CMP
CMPI
CMPU
CMPUI
Logical operation
Compare
Compare immediate
Compare unsigned
Compare unsigned immediate
AND
AND3
NOT
OR
OR3
XOR
XOR3
AND
AND 3-operand
Logical NOT
OR
OR 3-operand
Exclusive OR
Exclusive OR 3-operand
Arithmetic operation
ADD
ADD3
ADDI
ADDV
ADDV3
ADDX
NEG
SUB
SUBV
SUBX
Multiplication/division
Add
Add 3-operand
Add immediate
Add (with overflow checking)
Add 3-operand
Add with carry
Negate
Subtract
Subtract (with overflow checking)
Subtract with borrow
DIV
DIVU
MUL
REM
REMU
Shift
Divide
Divide unsigned
Multiply
Remainder
Remainder unsigned
SLL
SLL3
SLLI
SRA
SRA3
SRAI
SRL
SRL3
SRLI
Shift left logical
Shift left logical 3-operand
Shift left logical immediate
Shift right arithmetic
Shift right arithmetic 3-operand
Shift right arithmetic immediate
Shift right logical
Shift right logical 3-operand
Shift right logical immediate
(5) Instructions for the DSP function
Perform 32 bit
×
16 bit or 16 bit
×
16 bit multiplication or sum-
of-products calculation. These instructions also perform
rounding of the accumulator data or transfer between accu-
mulator and general-purpose register.
MACHI
Multiply-accumulate high-order
halfwords
Multiply-accumulate low-order
halfwords
Multiply-accumulate word and
high-order halfword
Multiply-accumulate word and
low-order halfword
Multiply high-order halfwords
Multiply low-order halfwords
Multiply word and high-order
halfword
Multiply word and low-order
halfword
Move from accumulator high-order word
Move from accumulator low-order word
Move from accumulator middle-order
word
Move to accumulator high-order word
Move to accumulator low-order word
Round accumulator
Round accumulator halfword
MACLO
MACWHI
MACWLO
MULHI
MULLO
MULWHI
MULWLO
MVFACHI
MVFACLO
MVFACMI
MVTACHI
MVTACLO
RAC
RACH
(6) EIT related instructions
Start trap or return from EIT processing.
RTE
TRAP
Return from EIT
Trap