參數(shù)資料
型號： M30L0R8000B0ZAQE
廠商： 意法半導(dǎo)體
英文描述： 256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory
中文描述： 256兆位（16Mb的x16插槽，多銀行，多層次，多突發(fā)）1.8V電源快閃記憶體
文件頁數(shù)： 19/83頁
文件大?。?/td> 1363K
代理商： M30L0R8000B0ZAQE
19/83
M30L0R8000T0, M30L0R8000B0
Two Bus Write cycles are required to issue the
Protection Register Program command.
The first bus cycle sets up the Protection
Register Program command.
The second latches the address and data to
be programmed to the Protection Register and
starts the Program/Erase Controller.
Read operations to the bank being programmed
output the Status Register content after the pro-
gram operation has started.
Attempting to program a previously protected Pro-
tection Register will result in a Status Register er-
ror.
The Protection Register Program cannot be sus-
pended. Dual operations between the Parameter
Bank and the Protection Register memory space
are not allowed (see
Table 15., Dual Operation
Limitations
for details).
The two Protection Register Locks are used to
protect the OTP segments from further modifica-
tion. The protection of the OTP segments is not re-
versible. Refer to
Figure 5., Protection Register
Memory Map
, and
Figure 5., Protection Register
Memory Map
, for details on the Lock bits.
See
APPENDIX C.
,
Figure 26., Protection Regis-
ter Program Flowchart and Pseudo Code
, for a
flowchart for using the Protection Register Pro-
gram command.
■
■
Set Configuration Register Command
The Set Configuration Register command is used
to write a new value to the Configuration Register.
Two Bus Write cycles are required to issue the Set
Configuration Register command.
The first cycle sets up the Set Configuration
Register command and the address
corresponding to the Configuration Register
content.
The second cycle writes the Configuration
Register data and the confirm command.
The Configuration Register data must be written
as an address during the bus write cycles, that is
A0 = CR0, A1 = CR1, …, A15 = CR15. Addresses
A16- A23 are ignored.
Read operations output the array content after the
Set Configuration Register command is issued.
The Read Electronic Signature command is re-
quired to read the updated contents of the Config-
uration Register.
■
■
Block Lock Command
The Block Lock command is used to lock a block
and prevent program or erase operations from
changing the data in it. All blocks are locked after
power-up or reset.
Two Bus Write cycles are required to issue the
Block Lock command.
The first bus cycle sets up the Block Lock
command.
The second Bus Write cycle latches the block
address and locks the block.
The lock status can be monitored for each block
using the Read Electronic Signature command.
Table 16.
shows the Lock Status after issuing a
Block Lock command.
Once set, the Block Lock bits remain set even after
a hardware reset or power-down/power-up. They
are cleared by a Block Unlock command.
Refer to the section, Block Locking, for a detailed
explanation.
See
APPENDIX
25., Locking Operations Flowchart and Pseudo
Code
, for a flowchart for using the Lock command.
■
■
C.
,
Figure
Block Unlock Command
The Block Unlock command is used to unlock a
block, allowing the block to be programmed or
erased.
Two Bus Write cycles are required to issue the
Block Unlock command.
The first bus cycle sets up the Block Unlock
command.
The second Bus Write cycle latches the block
address and unlocks the block.
The lock status can be monitored for each block
using the Read Electronic Signature command.
Table 16.
shows the protection status after issuing
a Block Unlock command.
Refer to the section, Block Locking, for a detailed
explanation
and
APPENDIX
25., Locking Operations Flowchart and Pseudo
Code
, for a flowchart for using the Block Unlock
command.
■
■
C.
,
Figure
Block Lock-Down Command
The Block Lock-Down command is used to lock-
down a locked or unlocked block.
A locked-down block cannot be programmed or
erased. The lock status of a locked-down block
cannot be changed when WP is low, V
IL
. When
WP is high, V
IH,
the lock-down function is disabled
and the locked blocks can be individually unlocked
by the Block Unlock command.
Two Bus Write cycles are required to issue the
Block Lock-Down command.
The first bus cycle sets up the Block Lock-
Down command.
■
相關(guān)PDF資料
PDF描述
M30L0R8000B0ZAQF CAP 0.1UF 50V 10% X7R DIP-2 BULK S-MIL-C-39014
M30L0R8000B0ZAQT 256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory
M30L0R8000B0ZAQ 256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory
M30L0R8000T0 256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory
M30L0R8000B0 256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M30L0R8000B0ZAQF 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory
M30L0R8000B0ZAQT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory
M30L0R8000T0 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory
M30L0R8000T0ZAQ 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory
M30L0R8000T0ZAQE 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory
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