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21. Intelligent I/O (Group 3 Communication Function)
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21.6.1 8-bit or 16-bit Clock Synchronous Serial I/O Mode (Group 3)
In 8-bit or 16-bit clock synchronous serial I/O mode, data is transmitted and received using the transfer
clock. When the internal clock is selected as the transfer clock, the channel 0 and channel 2 waveform
generation functions generate the transfer clock. ISTxD3, ISCLK3 and ISRxD3 share pins with OUTC30
to OUTC32 and are available in the 144-pin package only.
Table 21.41 lists specifications of clock synchronous serial I/O mode. Table 21.42 lists registers to be
used and their settings. Tables 21.43 and 21.44 list pin settings. Figure 21.50 and 21.51 shows an
example of transmit and receive operation.
Table 21.41 Clock Synchronous Serial I/O Mode (Group 3)
Item
Specification
Transfer Data Format
Transfer data :
8 bits or 16 bits long
Transfer Clock(1)
When the CKDIR bit in the G3MR register is set to "0" (internal clock) :
n : setting value of the G3PO0 register, 000116 to FFFD16
_ The G3PO0 register determines the bit rate and the transfer clock is generated in phase-
delayed waveform output mode of the channel 2 waveform generation function.
When the CKDIR bit is set to "1" (external clock) : input from the ISCLK3 pin
Transmit Start Condition(2)
Set registers associated with the waveform generation function and the G3MR register.
Then, set as written below after waiting at least one transfer clock cycle.
Set the TE bit in the G3CR register to "1" (transmit enable)
Set the TI bit in the G3CR register to "0" (data in the G3TB register)
Receive Start Condition
Set registers associated with the waveform generation function and the G3MR register.
Then, set as written below after waiting at least one transfer clock cycle.
Set the RE bit in the G3CR register to "1" (receive enable)
Set theTE bit to "1" (transmit enable)
Set the TI bit to "0" (data in the G3TB register)
Interrupt Request
While transmitting, one of the following conditions can be selected to set the
SIO3TR bit in the IIO10IR register to "1" (see Figure 10.14) :
_ When the IRS bit in the G3MR register is set to "0" (no data in the transmit buffer),
one transfer clock cycle after data transmission starts
_ When the IRS bit is set to "1" (reception completed),
15 transfer clock cycles after data transmission starts in 16-bit clock synchronous
serial I/O mode (set the DLS bit in the G3MR register to "0"), or
7 transfer clock cycles after data transmission starts in 8-bit clock clock synchronous
serial I/O mode (set the DLS bit to "1").
While receiving, the following condition can be selected to set the SIO3RR bit in the
IIO9IR register to "1" (see Figure 10.14) :
15.5 transfer clock cycles after data transmission starts in 16-bit clock synchronous
serial I/O mode, or
7.5 transfer clock cycles after data transmission starts in 8-bit clock synchronous
serial I/O mode
Error Detection
Overrun error(3)
This error occurs in 16-bit clock synchronous serial I/O mode when the 15th bit of
the next data is received before reading the G3RB register.
This error occurs in 8-bit clock synchronous serial I/O mode when the 7th bit of the
next data is received before reading the G3RB register.
Selectable Function
LSB first/MSB first
Select either bit 0 or bit 7 to transmit/receive data
ISTxD3 and ISRxD3 I/O polarity inverse
ISTxD3 pin output level and ISRxD3 pin input level are inversed
NOTES:
1. The transfer clock must be fBT3 divided by six or more.
2. Transmit interrupt request is generated when the TE bit is set to "1". Set the interrupt-associated
registers after setting the TE bit.
3. When an overrun error occurs, the G3RB register is indeterminate.
fBT3
2(n+2)