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| 型號(hào)： | M30826MH-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, MROM, 30 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 28/48頁(yè) |
| 文件大小： | 847K |
| 代理商： | M30826MH-XXXFP |
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1.4 REGISTER DESCRIPTION
Nine write-only registers provide several control and config-
uration options in the Extended Control Mode. These regis-
ters have no effect when the device is in the Non-Extended
Control Mode. Each register description below also shows the
Register Default State.
Calibration Register
Addr: 0h (0000b)
Write only (0x7FFF)
D15
D14
D13
D12
D11
D10
D9
D8
CAL
1
D7
D6
D5
D4
D3
D2
D1
D0
1
Bit 15
CAL: Calibration Enable. When this bit is set
1b, a command calibration cycle is initiated.
This function is exactly the same as issuing
a calibration using the CAL pin. See section
2.5.2.1, Initiating Calibration for details for
usage.
Default State: 0b
Bits 14:0
Must be set to 1b
Configuration Register
Addr: 1h (0001b)
Write only (0xB2FF)
D15
D14
D13
D12
D11
D10
D9
D8
1
0
nSD
DCS
DCP
nDE
OV
OED
D7
D6
D5
D4
D3
D2
D1
D0
1
Bit 15
Must be set to 1b
Bit 14
Must be set to 0b
Bit 13
nSD: Second DCLK Output. When this bit is
1b, the device only has one DCLK output and
one OR output. When this output is 0b, the
device has two identical DCLK outputs and no
OR output.
Default State: 1b
Bit 12
DCS: Duty Cycle Stabilizer. When this bit is set
to 1b, a duty cycle stabilization circuit is
applied to the clock input. When this bit is set
to 0b the stabilization circuit is disabled.
Default State: 1b
Bit 11
DCP: DDR Clock Phase. This bit only has an
effect in the DDR Mode. When this bit is set to
0b, the DCLK edges are time-aligned with the
data bus edges ("0° Phase"). When this bit is
set to 1b, the DCLK edges are placed in the
middle of the data bit-cells ("90° Phase"),
using the one-half speed DCLK shown in
Figure 4 as the phase reference.
Default State: 0b
Bit 10
nDE: DDR Enable. When this bit is set to 0b,
data bus clocking follows the DDR (Double
Data Rate) Mode whereby a data word is
output with each rising and falling edge of
DCLK. When this bit is set to a 1b, data bus
clocking follows the SDR (single data rate)
Mode whereby each data word is output with
either the rising or falling edge of DCLK , as
determined by the OutEdge bit.
Default State: 0b
Bit 9
OV: Output Voltage. This bit determines the
LVDS outputs' voltage amplitude and has the
same function as the OutV pin that is used in
the Non-Extended Control Mode. When this bit
is set to 1b, the standard output amplitude of
780 mV
P-P is used. When this bit is set to 0b,
the reduced output amplitude of 590 mV
P-P is
used.
Default State: 1b
Bit 8
OED: Output Edge and Demultiplex Control.
This bit has two functions. When the device is
in SDR Mode, this bit selects the DCLK edge
with which the data words transition in the
SDR Mode and has the same effect as the
OutEdge pin in the Non-Extended Control
Mode. When this bit is set to 1b, the data
outputs change with the rising edge of DCLK
+. When this bit is set to 0b, the data output
changes with the falling edge of DCLK+. When
the device is in DDR Mode, this bit selects the
Non-Demultiplexed Mode when set to 1b.
When the bit set to 0b, the device is
programmed into the 1:2 Demultiplexed Mode.
The 1:2 Demultiplexed Mode is the default
mode. In DDR Mode, DCLK has a 0° phase
relationship with the data.
Default State: 0b
Bits 7:0
Must be set to 1b
IMPORTANT NOTE:
It is recommended that this register
should only be written upon power-up initialization as writing
it may cause disturbance on the DCLK output as this signals
basic configuration is changed.
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ADC08D1520QML
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