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參數(shù)資料
| 型號： | M30823MW-XXXGP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, MROM, 30 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 30/48頁 |
| 文件大?。?/td> | 847K |
| 代理商： | M30823MW-XXXGP |
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Q- Channel Full-Scale Voltage Adjust
Addr: Bh (1011b)
Write only (0x807F)
D15
D14
D13
D12
D11
D10
D9
D8
(MSB)
Adjust Value
D7
D6
D5
D4
D3
D2
D1
D0
(LSB)
1
Bit 15:7
Full Scale Voltage Adjust Value. The input full-
scale voltage or gain of the I- Channel ADC is
adjusted linearly and monotonically with a 9 bit
data value. The adjustment range is ±20% of
the nominal 700 mV
P-P differential value.
0000 0000 0
560 mV
P-P
1000 0000 0
700 mV
P-P
1111 1111 1
840 mV
P-P
For best performance, it is recommended that
the value in this field be limited to the range of
0110 0000 0b to 1110 0000 0b. i.e., limit the
amount of adjustment to ±15%. The remaining
±5% headroom allows for the ADC's own full
scale variation. A gain adjustment does not
require ADC re-calibration.
Default State: 1000 0000 0b (no adjustment)
Bits 6:0
Must be set to 1b
Sample Clock Phase Fine Adjust
Addr: Eh (1110b)
Write only (0x00FF)
D15
D14
D13
D12
D11
D10
D9
D8
(MSB)
Fine Phase Adjust
(LSB)
D7
D6
D5
D4
D3
D2
D1
D0
1
Bits 15:8
Fine Phase Adjust. The phase of the ADC
sampling clock is adjusted linearly and
monotonically by the value in this field. 00h
provides a nominal zero phase adjustment,
while FFh provides a nominal 50 ps of delay.
Thus, each code step provides about 0.2 ps
of delay.
Default State: 0000 0000b
Bits 7:0
Must be set to 1b
Sample Clock Phase Intermediate/Coarse Adjust
Addr: Fh (1111b)
Write only (0x007F)
D15
D14
D13
D12
D11
D10
D9
D8
POL
(MSB) Coarse Phase Adjust
IPA
D7
D6
D5
D4
D3
D2
D1
D0
(LSB)
1
Bit 15
Polarity Select. When this bit is selected, the
polarity of the ADC sampling clock is
inverted.
Default State: 0b
Bits 14:10 Coarse Phase Adjust. Each code value in
this field delays the sample clock by
approximately 65 ps. A value of 00000b in
this field causes zero adjustment.
Default State: 00000b
Bits 9:7
Intermediate Phase Adjust. Each code value
in this field delays the sample clock by
approximately 11 ps. A value of 000b in this
field causes zero adjustment. Maximum
combined adjustment using Coarse Phase
Adjust and Intermediate Phase adjust is
approximately 2.1ns.
Default State: 000b
Bits 6:0
Must be set to 1b
Note Regarding Extended Mode Offset Correction
When using the I- Channel or Q- Channel Offset Adjust reg-
isters, the following information should be noted.
For offset values of +0000 0000 and -0000 0000, the actual
offset is not the same. By changing only the sign bit in this
case, an offset step in the digital output code of about 1/10th
of an LSB is experienced. This is shown more clearly in the
Figure below.
Note Regarding Clock Phase Adjust
This is a feature intended to help the system designer remove
small imbalances in clock distribution traces at the board level
when multiple ADCs are used. Please note, however, that
enabling this feature will reduce the dynamic performance
(ENOB, SNR SFDR) some finite amount. The amount of
degradation increases with the amount of adjustment applied.
The user is strongly advised to (a) use the minimal amount of
adjustment: and (b) verify the net benefit of this feature in his
system before relying on it.
30024730
FIGURE 11. Extended Mode Offset Behavior
www.national.com
36
ADC08D1520QML
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相關(guān)代理商/技術(shù)參數(shù) |
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| M30825MH-XXXGP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER |
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