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參數(shù)資料
| 型號(hào)： | M30823MW-XXXGP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, MROM, 30 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 22/48頁 |
| 文件大小： | 847K |
| 代理商： | M30823MW-XXXGP |
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It is important that no digital activity take place on any of
the digital input lines during the calibration process, except
that there must be a stable, constant frequency CLK signal
present and that SCLK may be active if the Enhanced
Mode is selected. Actions that are not allowed include but
are not limited to:
Changing OUTV
Changing OutEdge or SDATA sense
Changing between SDR and DDR
Changing FSE or ECE
Changing DCLK_RST
Changing SCS
Raising PD high
Raising CAL high
Doing any of these actions can cause faulty calibration.
1.1.2 Acquiring the Input
Data is acquired at the falling edge of CLK+ (pin 18) and the
digital equivalent of that data is available at the digital outputs
13 input clock cycles later for the DI and DQ output buses and
14 input clock cycles later for the DId and DQd output buses.
There is an additional internal delay called t
OD before the data
is available at the outputs. See the Timing Diagram. The AD-
C08D1520 will convert as long as the input clock signal is
present. The fully differential comparator design and the in-
novative design of the sample-and-hold amplifier, together
with self calibration, enables a very flat SINAD/ENOB re-
sponse beyond 1.5 GHz. The ADC08D1520 output data sig-
naling is LVDS and the output format is offset binary.
1.1.3 Control Modes
Much of the user control can be accomplished with several
control pins that are provided. Examples include initiation of
the calibration cycle, Power Down Mode and full scale range
setting. However, the ADC08D1520 also provides an Extend-
ed Control mode whereby a serial interface is used to access
register-based control of several advanced features. The Ex-
tended Control mode is not intended to be enabled and
disabled dynamically. Rather, the user is expected to employ
either the Non-Extended Control Mode or the Extended Con-
trol Mode at all times. When the device is in the Extended
Control Mode, pin-based control of several features is re-
placed with register-based control and those pin-based con-
trols are disabled. These pins are OutV (pin 3), OutEdge/DDR
(pin 4), FSR (pin 14) and DES (pin 127). See 1.2 NON-EX-
TENDED CONTROL/EXTENDED CONTROL for details on
the Extended Control Mode.
1.1.4 The Analog Inputs
The ADC08D1520 must be driven with a differential input sig-
nal. Operation with a single-ended signal is not recommend-
ed. It is important that the input signals are a.c. coupled to the
inputs.
Two full-scale range settings are provided with pin 14 (FSR).
A high on pin 14 causes an input full-scale range setting of a
higher V
IN input level, while grounding pin 14 causes an input
full-scale range setting of a reduced V
IN input level. The full-
scale range setting operates equally on both ADCs.
In the Extended Control Mode, the Input Full-Scale Voltage
Adjust register allows the input full-scale range to be adjusted
as described in 1.4 REGISTER DESCRIPTION and 2.3 THE
1.1.5 Clocking
The ADC08D1520 must be driven with an a.c. coupled, dif-
ferential clock signal. 2.4 THE CLOCK INPUTS describes the
use of the clock input pins. A differential LVDS output clock is
available for use in latching the ADC output data into whatever
device is used to receive the data.
The ADC08D1520 offers input and output clocking options.
These options include a choice of Dual Edge Sampling (DES)
or "interleaved mode" where the ADC08D1520 performs as a
single device converting at twice the input clock rate, a choice
of which DCLK edge the output data transitions on, and a
choice of Single Data Rate (SDR) or Double Data Rate (DDR)
outputs.
The ADC08D1520 also has the option to use a duty cycle
corrected clock receiver as part of the input clock circuit. This
feature is enabled by default and provides improved ADC
clocking especially in the Dual-Edge Sampling Mode
(DES). This circuitry allows the ADC to be clocked with a
signal source having a duty cycle ratio of 20%/80% (worst
case) for both the Non-DES and the Dual Edge Sampling
Modes.
1.1.5.1 Dual-Edge Sampling
The DES Mode allows one of the ADC08D1520's inputs (I- or
Q- Channel) to be sampled by both ADCs. One ADC samples
the input on the positive edge of the input clock and the other
ADC samples the same input on the other edge of the input
clock. A single input is thus sampled twice per input clock cy-
cle, resulting in an overall sample rate of twice the input clock
frequency, or 3 GSPS with a 1.5 GHz input clock.
In this mode, the outputs must be carefully interleaved to re-
construct the sampled signal. If the device is programmed into
the 1:2 Demultiplex Mode while in DES Mode, the data is ef-
fectively Demultiplexed 1:4. If the input clock is 1.5 GHz, the
effective sampling rate is doubled to 3 GSPS and each of the
4 output buses have a 750 MHz output rate. All data is avail-
able in parallel. To properly reconstruct the sampled wave-
form, the four bytes of parallel data that are output with each
clock are in the following sampling order from the earliest to
the latest and must be interleaved as such: DQd, DId, DQ, DI.
Table 1 indicates what the outputs represent for the various
sampling possibilities. If the device is programmed into the
Non-Demultiplex Mode, two bytes of parallel data are output
with each edge of the clock in the following sampling order,
from the earliest to the latest: DQ, DI. See Table 2.
In the Non-Extended Control Mode of operation only the I-
channel input can be sampled in the DES Mode. In the
Extended Control Mode of operation, the user can select
which input is sampled.
The ADC08D1520 also includes an automatic clock phase
background calibration feature which can be used in DES
Mode to automatically and continuously adjust the clock
phase of the I- and Q- channel. This feature removes the need
to adjust the clock phase setting manually and provides opti-
mal Dual-Edge Sampling ENOB performance.
IMPORTANT NOTE:
The background calibration feature in
DES Mode does not replace the requirement for calibration if
a large swing in ambient temperature is experienced by the
device.
29
www.national.com
ADC08D1520QML
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