deveopmen
UARTi Special Mode Register
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (100-pin version) group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
158
P1
3
P1
2
IC1
P9
3(
SS
3
)
P9
0(
CLK
3
)
P9
1(
RxD
3
)
P9
2(
TxD
3
)
IC2
P9
3(
SS
3
)
P9
0(
CLK
3
)
P9
1(
STxD
3
)
P9
2(
SRxD
3
)
IC3
P9
3(
SS
3
)
P9
0(
CLK
3
)
P9
1(
STxD
3
)
P9
2(
SRxD
3
)
M16C/80 (M)
M16C/80 (S)
M16C/80 (S)
M :Master
S :Slave
(2) Serial Interface Special Function
UART 3 and UART4 can control communications on the serial bus using the SSi input pins (Figure
1.20.5). The master outputting the transfer clock transfers data to the slave inputting the transfer clock. In
this case, in order to prevent a data collision on the bus, the master floats the output pin of other slaves/
masters using the SSi input pins. Figure 1.20.6 shows the structure of UARTi special mode register 3
(addresses 0325
16
and 02F5
16
[i = 3 or 4]) which controls this mode.
SSi input pins function between the master and slave are as follows.
Figure 1.20.5 Serial bus communication control example using the SSi input pins
< Slave Mode (STxDi and SRxDi are selected, DINC = 1) >
When an H level signal is input to an SSi input pin, the STxDi and SRxDi pins both become high
impedance, hence clock input is ignored. When an "L" level signal is input to an SSi input pin, clock
input becomes effective and serial communications are enabled. (i = 3 or 4)
< Master Mode (TxDi and RxDi are selected, DINC = 0) >
The SSi input pins are used with a multiple master system. When an SSi input pin is H level, transmis-
sion has priority and serial communications are enabled. When an L signal is input to an SSi input pin,
another master exists, and the STxDi, SRxDi and CLKi pins all become high impedance. Moreover,
the trouble error interrupt request bit becomes “1”. Communications do not stop even when a trouble
error is generated during communications. To stop communications, set bits 0, 1 and 2 of the UARTi
transmission-reception mode register (address 0328
16
and 02F8
16
[i = 3 or 4]) to “0”.
The trouble error interrupt is used by both the bus collision interrupt and start/stop condition detection
interrupts, but the trouble error interrupt itself can be selected by setting bit 0 of UARTi special mode
register 3 (address 0325
16
and 02F5
16
[i = 3 or 4]) to “1”.
When the trouble error flag is set to “0”, output is restored to the clock output and data output pins. In
the master mode, if an SSi input pin is H level, “0” can be written for the trouble error flag. When an SSi
input pin is L level, “0” cannot be written for the trouble error flag. In the slave mode, the “0” can be
written for the trouble error flag regardless of the input to the SSi input pins.