Rev.1.30
Oct 06, 2004
page 129 of 249
M306V0ME-XXXFP, M306V0EEFP
Table 2.11.10 Features in I2C mode
In the first place, the control bits related to the I2C-BUS interface are explained.
Setting 1 in the I2C mode selection bit (bit 0) goes the circuit to achieve the I2C-BUS (simplified I2C-BUS)
interface effective. Table 2.11.10 shows the relation between the I2C mode selection bit and respective
control workings.
Since this function uses clock-synchronous serial I/O mode, be sure to set this bit to “0” in UART mode.
Figure 2.11.32 shows the functional block diagram for I2C mode. Setting “1” in the I2C mode selection bit
(IICM) causes ports P70, P67, P71, and P72 selected by bits 0 and 1 of the peripheral mode register
(address 027D16) to work as data transmission-reception terminals; SDA1, SDA2, clock input-output ter-
minals; SCL1, SCL2 respectively. A delay circuit is added to the SDA transmission output, so the SDA
output changes after SCL fully goes to L. An attempt to read Port P71 (SCL1), P72 (SCL2) results in
getting the terminal’s level regardless of the content of the port direction register. The initial value of SDA
transmission output in this mode goes to the value set in port (P70 when using SDA1, P67 when using
SDA2, P70 when using both SDA1 and SDA2). The interrupt factors of the bus collision detection inter-
rupt, UART2 transmission interrupt, and of UART2 reception interrupt turn to the start/stop condition
detection interrupt, acknowledgment non-detection (NACK) interrupt, and acknowledgment detection
(ACK) interrupt respectively.
The start condition detection interrupt refers to the interrupt that occurs when the falling edge of the SDA
terminal is detected with the SCL terminal staying “H.” The stop condition detection interrupt refers to the
interrupt that occurs when the rising edge of the SDA terminal is detected with the SCL terminal staying
“H”. The bus busy flag (bit 2 of the special UART2 mode register) is set to “1” by the start condition
detection, and set to “0” by the stop condition detection. The acknowledgment non-detection interrupt
refers to the interrupt that occurs when the SDA terminal’s level is detected still staying “H” at the rising
edge of the 9th transmission clock. The acknowledgment detection interrupt refers to the interrupt that
occurs when SDA terminal’s level is detected already went to “L” at the 9th transmission clock. Also,
assigning 1 1 0 1 (UART2 reception) to the DMA1 request factor selection bits provides the means to start
up the DMA transfer by the effect of acknowledgment detection.
Function
Normal mode
I2C mode
Factor of interrupt number 15
UART2 transmission
No acknowledgment detection (NACK) (Note)
Factor of interrupt number 16
UART2 reception
Start condition detection or stop
condition detection (Note)
UART2 transmission output delay
Not delayed
Delayed
P70 at the time when UART2 is in use
TxD2 (output)
SDA1 (input/output) (Note 3)
P71 at the time when UART2 is in use
RxD2 (input)
SCL1 (input/output) (Note 3)
P72 at the time when UART2 is in use
CLK2 (CMOS)
SCL2 (N-channel open-drain) (Note 3)
DMA1 factor at the time when 1 1 0 1
is assigned to the DMA request factor
selection bits
UART2 reception
Acknowledgment detection (ACK)
Noise filter width
15 ns
50 ns
Reading P71/P72
Reading the terminal
when 0 is assigned to
the direction register
Reading the terminal regardless of the
value of the direction register (Note 3)
1
2
3
4
5
6
7
8
9
Notes 1: Make the settings given below when I 2C
mode is in use.
Set 0 1 0 in bits 2, 1, 0 of the UART2
transmission-reception mode register.
Disable the RTS/CTS function.
Choose the LSB First function.Follow
the steps given below to switch from
a factor to another.
2: Follow the steps given below to switch
from a factor to another.
1. Disable the interrupt of the
corresponding number.
2. Switch from a factor to another.
3. Reset the interrupt request flag
of the corresponding number.
4. Set an interrupt level of the
corresponding number.
3: In I2C mode and when setting as I 2C-BUS
interface ports.
Factor of interrupt number 10
Bus collision detection
Acknowledgment detection (ACK) (Note)
10
Initial value of UART2 output
H level (when 0 is
assigned to the CLK
polarity select bit)
The value set in latch P7 0/P67 when the port
is selected (Note 3)
11
P67 input/output
12
P67 (CMOS)
SDA2 (N-channel open-drain) (Note 3)