參數(shù)資料
型號(hào): M30624MGA-379FP
廠商: Mitsubishi Electric Corporation
英文描述: SYSTEM BASIC CHIPS
中文描述: 單片16位CMOS微機(jī)
文件頁(yè)數(shù): 135/274頁(yè)
文件大?。?/td> 3495K
代理商: M30624MGA-379FP
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Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 Special Mode Register
135
UART2 Special Mode Register
The UART2 special mode register (address 0377
16
) is used to control UART2 in various ways.
Figure 1.16.26 shows the UART2 special mode register.
Bit 0 of the UART special mode register (0377
16
) is used as the I
2
C mode select bit.
Setting “1” in the I
2
C mode select bit (bit 0) goes the circuit to achieve the I
2
C bus (simplified I
2
C bus)
interface effective.
Table 1.16.9 shows the relation between the I
2
C mode select bit and respective control workings.
Since this function uses clock-synchronous serial I/O mode, set this bit to “0” in UART mode.
Figure 1.16.26. UART2 special mode register
UART2 special mode register
Symbol
0377
16
Wh00
16
b7
b6
b5
b4 b3
b2
b1
b0
nBit
Bit
symbol
W
R
A
Function
(During UART mode)
(Duriserial I/O mode)
ABSCS
ACSE
SSS
I2C mode select bit
Bus busy flag
0 : STOP condition detected
1 : START condition detected
SCLL sync output
Bus collision detect
sampling
clock select bit
Arbitration lost detecting
flag control bit
0 : Normal mode
0 : Update per bit
1 : Update per byte
IICM
ABC
BBS
LSYN
0 : Ordinary
0 : Disabled
Transmit start condition
Must always be “0”
0 : Rising edge of transfer
clock
1 : Under flow signal of timer A0
Auto clear function
A
AA
AA
A
A
A
0 : bus collision
Must always be “0”
Must always be “0”
Must always be “0”
Must always be “0”
Must always be “0”
Must always be “0”
Note 1: bit = “0”, UART2 special mode register 3 (U2SMR3 at address 0375
16
) bits 7 to 5 (DL2 to DL0 = SDA
digital delay setup bits) are initialized to “000”, with the analog delay circuit selected. Also, when SDDS
Note 3: = “0”, the U2SMR3 register cannot be read or written to.
only the digital delay value is effective.
(Note1)
A
A
SDDS
SDA digital delay select
bit (Note 2, Note 3)
Must always be “0”
0 : Analog delay output
1 : Digital delay output
not using I C mode)
UART2 special mode register 3 (I C bus exclusive use register)
Symbol
U2SMR3
Address
0375
16
When reset
Indeterminate
(However, when SDDS = “1”, the initial value is “00
16
”)
b7
b6 b5
b4
b3
b2
b1
b0
Bit name
Bit
symbol
W
R
Function
(I C bus exclusive use register)
DL2
SDA digital delay setup
bit
(Note 1, Note 2, Note 3,
Note 4)
DL0
DL1
A
A
A
A
0 0 0 : Analog delay is selected
0 0 1 : 2 cycle of 1/f(X
IN
)
0 1 0 : 3 cycle of 1/f(X
IN
)
0 1 1 : 4 cycle of 1/f(X
IN
)
1 0 0 : 5 cycle of 1/f(X
IN
)
1 0 1 : 6 cycle of 1/f(X
IN
)
1 1 0 : 7 cycle of 1/f(X
IN
)
1 1 1 : 8 cycle of 1/f(X
IN
)
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate. However, when SDDS = “1”, the value “0” is read out (Note 1)
2
b7 b6 b5
Note 1: This bit can be read or written to when UART2 special mode register (U2SMR at address 0377
16
) bit
7 (SDDS: SDA digital delay select bit) = “1”. When the initial value of UART2 special mode register 3
(U2SMR3) is read after setting SDDS = “1”, the value is “00
”. When writing to UART2 special mode
register 3 (U2SMR3) after setting SDDS = “1”, be sure to write 0's to bits 0–4. When SDDS = “0”,
this register cannot be written to; when read, the value is indeterminate.
Note 2: These bits are initialized to “000” when SDDS = “0”, with the analog delay circuit selected. After a reset,
these bits are set to “000”, with the analog delay circuit selected. However, because these bits can be
read only when SDDS = “1”, the value read from these bits when SDDS = “0” is indeterminate.
Note 3: When analog delay is selected, only the analog delay value is effective; when digital delay is selected,
only the digital delay value is effective.
Note 4: The amount of delay varies with the load on SCL and SDA pins. Also, when using an external clock, the
amount of delay increases by about 100 ns, so be sure to take this into account when using the device.
Digital delay is
selected
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