參數(shù)資料
型號: M30624FGAFP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù): 6/40頁
文件大小: 3893K
代理商: M30624FGAFP
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
11
Central Processing Unit (CPU)
The CPU has a total of 13 registers shown in Figure 1.4.1. Seven of these registers (R0, R1, R2, R3, A0,
A1, and FB) come in two sets; therefore, these have two register banks.
(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and
arithmetic/logic operations.
Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H),
and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can
use as 32-bit data registers (R2R0/R3R1).
(2) Address registers (A0 and A1)
Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data
registers. These registers can also be used for address register indirect addressing and address register
relative addressing.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
H
L
b15
b8 b7
b0
R0(Note)
H
L
b15
b8 b7
b0
R1(Note)
R2(Note)
b15
b0
R3(Note)
b15
b0
A0(Note)
b15
b0
A1(Note)
b15
b0
FB(Note)
b15
b0
Data
registers
Address
registers
Frame base
registers
b15
b0
b15
b0
b15
b0
b15
b0
b19
b0
b19
H
L
Program counter
Interrupt table
register
User stack pointer
Interrupt stack
pointer
Static base
register
Flag register
PC
INTB
USP
ISP
SB
FLG
Note: These registers consist of two register banks.
C
D
Z
S
B
O
I
U
IPL
Figure 1.4.1. Central processing unit register
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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