Mitsubishi microcomputers
M16C / 62 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode (Flash Memory Version)
238
Flash memory control register 0
Symbol
FMR0
Address
03B7
16
When reset
XX000001
2
b7
b6
b5
b4
b3
b2 b1
b0
FMR00
Bit symbol
Bit name
Function
RW
0: Busy (being written or erased)
1: Ready
CPU rewrite mode
select bit (Note 1)
0: Normal mode
(Software commands invalid)
1: CPU rewrite mode
(Software commands acceptable)
FMR01
0: Boot ROM area is accessed
1: User ROM area is accessed
Lock bit disable bit
(Note 2)
0: Block lock by lock bit data is
enabled
1: Block lock by lock bit data is
disabled
Flash memory reset bit
(Note 3)
0: Normal operation
1: Reset
Nothing is assigned.
When write, set "0". When read, values are indeterminate.
User ROM area select bit (
Note 4) (Effective in only
boot mode)
FMR02
FMR03
FMR05
0
Note 1: For this bit to be set to
“
1
”
, the user needs to write a
“
0
”
and then a
“
1
”
to
it in succession. When it is not this procedure, it is not enacted in
“
1
”
.
This is necessary to ensure that no interrupt or DMA transfer will be
executed during the interval. Use the control program except in the
internal flash memory for write to this bit.
Note 2: For this bit to be set to
“
1
”
, the user needs to write a
“
0
”
and then a
“
1
”
to
it in succession when the CPU rewrite mode select bit =
“
1
”
. When it is
not this procedure, it is not enacted in
“
1
”
. This is necessary to ensure
that no interrupt or DMA transfer will be executed during the interval.
Note 3: Effective only when the CPU rewrite mode select bit = 1. Set this bit to 0
subsequently after setting it to 1 (reset).
Note 4: Use the control program except in the internal flash memory for write to
this bit.
A
A
A
A
A
A
A
A
A
A
A
A
A
A
AA
A
A
RY/BY status flag
Flash memory control register 1
Symbol
FMR1
Address
03B6
16
When reset
XXXX0XXX
2
A
R
RW
b7
b6
b5 b4
b3
b2
b1
b0
Bit symbol
Bit name
Function
Flash memory power
supply-OFF bit (Note)
0: Flash memory power supply is
connected
1: Flash memory power supply-off
FMR13
0
Note : For this bit to be set to
“
1
”
, the user needs to write a
“
0
”
and then a
“
1
”
to
it in succession. When it is not this procedure, it is not enacted in
“
1
”
.
This is necessary to ensure that no interrupt or DMA transfer will be
executed during the interval. Use the control program except in the
internal flash memory for write to this bit.
During parallel I/O mode,programming,erase or read of flash memory is
not controlled by this bit,only by external pins.
A
AA
0
0
0
0
0
Reserved bit
Must always be set to
“
0
”
A
Reserved bit
Must always be set to
“
0
”
Reserved bit
Must always be set to
“
0
”
0
Figure 1.29.1. Flash memory control registers
Bit 3 of the flash memory control register 1 turns power supply to the internal flash memory on/off. When
this bit is set to
“
1
”
, power is not supplied to the internal flash memory, thus power consumption can be
reduced. However, in this state, the internal flash memory cannot be accessed. To set this bit to
“
1
”
, it is
necessary to write
“
0
”
and then write
“
1
”
in succession. Use this bit mainly in the low speed mode (when
X
CIN
is the block count source of BCLK).
When the CPU is shifted to the stop or wait modes, power to the internal flash memory is automatically shut
off. It is reconnected automatically when CPU operation is restored. Therefore, it is not particularly neces-
sary to set flash memory control register 1.
Figure 1.29.2 shows a flowchart for setting/releasing the CPU rewrite mode. Figure 1.29.3 shows a flow-
chart for shifting to the low speed mode. Always perform operation as indicated in these flowcharts.