Mitsubishi microcomputers
M16C / 62 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
35
Table 1.12.4. Operation of RD, WR, and BHE signals
Data bus width
Status of external data bus
Write 1 byte of data to odd address
Read 1 byte of data from odd address
Write 1 byte of data to even address
Read 1 byte of data from even address
Write data to both even and odd addresses
Read data from both even and odd addresses
Write 1 byte of data
Read 1 byte of data
RD
H
L
H
L
H
L
H
L
BHE
L
L
H
H
L
L
Not used
WR
L
H
L
H
L
H
L
H
A0
H
H
L
L
L
H / L
H / L
8-bit
(BYTE = “H”)
16-bit
(BYTE = “L”)
Not used
Status of external data bus
Read data
Write 1 byte of data to even address
Write 1 byte of data to odd address
Write data to both even and odd addresses
WRH
H
H
L
L
WRL
H
L
H
L
RD
L
Data bus width
16-bit
(BYTE = “L”)
H
H
H
Table 1.12.3. Operation of RD, WRL, and WRH signals
(3) Read/write signals
With a 16-bit data bus (BYTE pin =“L”), bit 2 of the processor mode register 0 (address 0004
16
) select the
combinations of RD, BHE, and WR signals or RD, WRL, and WRH signals. With an 8-bit data bus (BYTE
pin = “H”), use the combination of RD, WR, and BHE signals. (Set bit 2 of the processor mode register 0
(address 0004
16
) to “0”.) Tables 1.12.3 and 1.12.4 show the operation of these signals.
After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically selected.
When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of the
processor mode register 0 (address 0004
16
) has been set (Note).
Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect
register (address 000A
16
) to “1”.
(4) ALE signal
The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the
ALE signal falls.
When BYTE pin = “H”
When BYTE pin = “L”
ALE
Address
Data (Note 1)
Address (Note 2)
D
0
/A
0
to D
7
/A
7
A
8
to A
19
ALE
Address
Data (Note 1)
Address
D
0
/A
1
to D
7
/A
8
A
9
to A
19
Address
A
0
Note 1: Floating when reading.
Note 2: When multiplexed bus for the entire space is selected, these are I/O ports.
Figure 1.12.2. ALE signal and address/data bus