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| 型號(hào)： | M30240M6-XXXXFP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件頁(yè)數(shù)： | 209/231頁(yè) |
| 文件大?。?/td> | 3508K |
| 代理商： | M30240M6-XXXXFP |
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60
Mitsubishi microcomputers
M30240 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Specifications REV. G
Specifications in this manual are tentative and subject to change
DMAC
1.2.19 DMAC
This microcomputer has two DMAC (direct memory access controller) channels that allow data to be
sent to memory without using the CPU.Table 1.15 shows the DMAC specifications. Figure 1.53 shows
the DMAC.
Table 1.15:
DMAC Specifications
Note: DMA transfers are not affected by the interrupt enable flag (Iflag) of any interrupt or by the interrupt priority level.
Item
Specification
Number of channels
2 (cycle steal method)
Transfer memory space
From any SFR, RAM, or ROM address to a fixed address
From a fixed address to any SFR or RAM address
From a fixed address to a fixed address
(Note that DMA-related registers [002016 to 003F16] cannot be accessed)
Maximum number of bytes
transferred
128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
DMA request sources
Falling edge of INT0 or INT1 (INT0 can be selected by DMA0, INT1 by DMA1)
Timer A0 to timer A4
Timer B0 to timer B1
UART0 transmission and reception
UART1 transmission and reception
UART2 transmission and reception
A-D conversion complete
USB function
Software triggers
Channel priority
DMA0 takes precedence if DMA0 and DMA1 requests are generated simultaneously
Transfer unit
8 bits or 16 bits
Transfer address direction
forward/fixed (forward direction cannot be specified for both source and destination
simultaneously)
Transfer modes
Single transfer mode
The DMA enable bit is cleared and transfer ends when an underflow occurs in the
transfer counter.
Repeat transfer mode
When an underflow occurs in the transfer counter, the value in the transfer counter
reload register is loaded into the transfer counter and the DMA transfer is repeated
DMA interrupt request generation
timing
When an underflow occurs in the transfer counter
DMA startup
Single transfer mode
Transfer starts when the DMA is requested after “1” is written to the DMA enable bit
Repeat transfer mode
Transfer starts when the DMA is requested after “1” is written to the DMA enable bit
or after an underflow occurs in the transfer counter
DMA shutdown
When “0” is written to the DMA enable bit
When, in single transfer mode, an underflow occurs in the transfer counter
Forward address pointer and
reload timing for transfer counter
When DMA transfer starts, the value of whichever of the source or destination pointer that is set
up as the forward pointer is loaded into the forward address pointer. The value in the transfer
counter reload register is loaded into the transfer counter.
Writing to register
Registers specified for forward direction transfer are always write-enabled.
Registers specified for fixed address transfer are write-enabled when the DMA enable bit is “0”.
Reading the register
Can be read at any time. However, when the DMA enable bit is “1”, reading the register sets up
as the forward register is the same as reading the value of the forward address pointer.
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| M30240M6-XXXXFP | 16-BIT, OTPROM, MICROCONTROLLER, PQFP80 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M30240M7 | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30240M7-XXXFP | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30240M8 | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30240M8-XXXFP | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30240M9 | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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