參數(shù)資料
型號： M30240M6-XXXFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP80
封裝： 0.80 MM PITCH, PLASTIC, QFP-80
文件頁數(shù)： 87/139頁
文件大?。?/td> 1453K
代理商： M30240M6-XXXFP
51
Mitsubishi microcomputers
M30240 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Specifications REV. G
Specifications in this manual are tentative and subject to change
Universal Serial Bus
1.2.18.4.6 USB Interrupt Enable Registers 1 and 2
The USB Interrupt Enable Registers 1 and 2, shown in Figure 1.36 and Figure 1.37, are used to enable the
corresponding interrupt status conditions that can generate a USB Function Interrupt. When the bit to a cor-
responding interrupt condition is “0”, that condition does not generate a USB function interrupt. When the bit
is a “1”, that condition can generate a USB function interrupt. At reset, all USB function interrupt status condi-
tions are enabled.
Figure 1.36: USB Interrupt Enable Register 1
Figure 1.37: USB Interrupt Enable Register 2
USB Interrupt Enable Register 1
Symbol
Address
When reset
USBIE1
030416
FF16
Bit name
Bit symbol
b7
b6
b5
b4
b3
b2
b1
b0
Function
W
R
Reserved
Must always be set to "1"
INTEN0
INTEN2
INTEN3
INTEN4
INTEN5
INTEN6
INTEN7
USB Endpoint 0 Interrupt
Enable Bit
USB Endpoint 1 IN
Interrupt Enable Bit
USB Endpoint 1 OUT
Interrupt Enable Bit
USB Endpoint 2 IN
Interrupt Enable Bit
USB Endpoint 2 OUT
Interrupt Enable Bit
USB Endpoint 3 IN
Interrupt Enable Bit
USB Endpoint 3 OUT
Interrupt Enable Bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
1
USB Interrupt Enable Register 2
Symbol
Address
When reset
USBIE2
030516
3316
Bit name
Bit symbol
b7
b6
b5
b4
b3
b2
b1
b0
Function
W
R
Reserved
Must always be set to "0"
INTEN8
INTEN9
USB Endpoint 4 IN
Interrupt Enable Bit
USB Endpoint 4 OUT
Interrupt Enable Bit
USB Overrun/Underrun
Interrupt Enable Bit
0 : Interrupt disabled
1 : Interrupt enabled
INTEN12
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Reserved
Must always be set to "1"
Reserved
Must always be set to "0"
0 0 1
0 0
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