Serial I/O
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Preliminary Specifications REV.E
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30220 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
87
Serial I/O
Serial I/O is configured as three channels: UART0, UART1, UART2.
UART0 to 2
UART0, UART1 and UART2 each have an exclusive timer to generate a transfer clock, so they operate
independently of each other.
Figure 1.15.1 shows the block diagram of UART0, UART1 and UART2. Figures 1.15.2 and 1.15.3 show
the block diagram of the transmit/receive unit.
UARTi (i = 0 to 2) has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous
serial I/O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses
03A0
16
, 03A8
16
and 0378
16
) determine whether UARTi is used as a clock synchronous serial I/O or as a
UART. Although a few functions are different, UART0, UART1 and UART2 have almost the same functions.
UART2, in particular, is used for the SIM interface with some extra settings added in clock-asynchronous
serial I/O mode (Note). It also has the bus collision detection function that generates an interrupt request if
the TxD pin and the RxD pin are different in level.
Table 1.15.1 shows the comparison of functions of UART0 through UART2, and Figures 1.15.4 to 1.15.8
show the registers related to UARTi.
Note: SIM : Subscriber Identity Module
Note 1: Only when clock synchronous serial I/O mode.
Note 2: Only when clock synchronous serial I/O mode and 8-bit UART mode.
Note 3: Only when UART mode.
Note 4: Using for SIM interface.
UART0
UART1
UART2
Function
CLK polarity selection
Continuous receive mode selection
LSB first / MSB first selection
Impossible
Transfer clock output from multiple
pins selection
Impossible
Impossible
Serial data logic switch
Impossible
Sleep mode selection
Impossible
Impossible
TxD, RxD I/O polarity switch
Impossible
Possible
CMOS output
TxD, RxD port output format
CMOS output
N-channel open-drain
output
Impossible
Parity error signal output
Impossible
Impossible
Bus collision detection
Impossible
Possible
Possible
(Note 1)
Possible
(Note 1)
Possible
(Note 1)
Possible
(Note 3)
Possible
(Note 1)
Possible
(Note 1)
Possible
(Note 1)
Possible
(Note 1)
Possible
(Note 3)
Possible
(Note 1)
Possible
(Note 2)
Possible
(Note 1)
Possible
(Note 4)
Possible
(Note 4)
Table 1.15.1. Comparison of functions of UART0 through UART2