UART2 Special Mode Register 2
deeopmen
Preliminary Specifications REV.E
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30220 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
121
IICM=1
and IICM2=0
IICM=1
and IICM2=0
IICM=0
or
IICM2=1
IICM=0
or IICM2=1
To DMA0, DMA1
To DMA0
I/0
Noize
P7
1
/RXD
2
/SCL
Reception register
UART2
CLK
control
UART2
IICM=1
Noize
UART2
IICM=0
P7
2
/CLK
2
D
T
Q
D
T
Q
UART2
R
IICM=1
IICM=0
IICM=0
IICM=1
S
R
Q
R
S
SWC
Falling of 9th pulse
SWC2
Start condition detection
Stop condition detection
Falling edge
detection
L-synchronous
Data register
Selector
Internal clock
External clock
Selector
I/0
Timer
Port reading
*
With IICM set to 1, the port terminal is to be readable
even if 1 is assigned to P7
1
of the direction register.
Bus
busy
UART2 transmission/
NACK interrupt
request
UART2 reception/ACK interrupt request
DMA1 request
NACK
ACK
IICM=1
IICM=0
Bus collision
detection
9th pulse
Bus collision/start, stop condition detection
interrupt request
I/0
delay
Noize
UART2
P7
0
/TXD
2
/SDA
D
T
Q
UART2
IICM=1
IICM=0
ALS
Selector
Timer
Arbitration
Transmission register
Functions available in I
2
C mode are shown in Figure 1.15.29 — a functional block diagram.
Bit 3 of the UART2 special mode register 2 (address 0376
16
) is used as the SDA output stop bit. Setting
this bit to "1" causes an arbitration loss to occur, and the SDA pin turns to high-impedance state the
instant when the arbitration loss detection flag is set to "1".
Bit 1 of the UART2 special mode register 2 (address 0376
16
) is used as the clock synchronization bit.
With this bit set to "1" at the time when the internal SCL is set to "H", the internal SCL turns to "L" if the
falling edge is found in the SCL pin; and the baud rate generator reloads the set value, and start counting
within the "L" interval. When the internal SCL changes from "L" to "H" with the SCL pin set to "L", stops
counting the baud rate generator, and starts counting it again when the SCL pin turns to "H". Due to this
function, the UART2 transmission-reception clock becomes the logical product of the signal flowing
through the internal SCL and that flowing through the SCL pin. This function operates over the period
from the moment earlier by a half cycle than falling edge of the UART2 first clock to the rising edge of the
ninth bit. To use this function, choose the internal clock for the transfer clock.
Bit 2 of the UART2 special mode register 2 (0376
16
) is used as the SCL wait output bit. Setting this bit to
"1" causes the SCL pin to be fixed to "L" at the falling edge of the ninth bit of the clock. Setting this bit to
"0" frees the output fixed to "L".
Figure 1.15.29. Functional block diagram for I
2
C mode