247
UART
M
i
t
s
u
M
S
b
i
s
3
M
h
0
I
C
i
m
2
R
i
1
O
c
r
8
C
o
c
o
G
M
m
p
r
P
u
t
u
T
e
r
p
R
s
o
U
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
O
E
(2) Transfer rate
The divide-by-16 frequency, resulting from division in the bit rate generator (BRG), becomes the trans-
fer rate. The count source for the bit rate generator can be selected from f
1
, f
8
, f
32
, and the input from
the CLK pin. Clocks f
1
, f
8
, f
32
are derived by dividing the CPU’s main clock by 1, 8, and 32 respec-
tively.
Table 2.5.2. Example of baud rate setting
Table 2.5.3. Error detection
Type of error
(3) An error detection
In clock-asynchronous serial I/O mode, detect errors are shown in Table 2.5.3.
Baud rate
(bps)
BRG's
count source
System clock : 10MHz
System clock : 7.3728MHz
BRG's set value : n
Actual time (bps)
BRG's set value : n
600
1200
2400
4800
9600
14400
19200
28800
31250
f
8
f
8
f
8
f
1
f
1
f
1
f
1
f
1
f
1
129 (81
16
)
64 (40
16
)
32 (20
16
)
129 (81
16
)
64 (40
16
)
42 (2A
16
)
32 (20
16
)
21 (15
16
)
19 (13
16
)
600
1201
2367
4807
9615
14534
18939
28409
31250
95 (5F
16
)
47 (2F
16
)
23 (17
16
)
95 (5F
16
)
47 (2F
16
)
31 (1F
16
)
23 (17
16
)
15 (F
16
)
600
1200
2400
4800
9600
14400
19200
28800
Actual time (bps)
When the flag turns on
Description
How to clear the flag
This error occurs when the
next data lines up before the
content of the UARTi receive
buffer register is read.
The next data is written to the
UARTi receive buffer register.
The UARTi receive interrupt
request bit does not go to “1”.
This error occurs when the
stop bit falls short of the set
number of stop bits.
With parity enabled, this error
occurs when the total number
of 1's in character bits and the
parity bit is different from the
specified number.
This flag turns on when any
error (overrun, framing, or
parity) is detected.
The error is detected
when data is
transferred from the
UARTi receive register
to the UARTi receive
buffer register.
Set the serial I/O mode select
bits to “000
2
”.
Set the receive enable bit to
“0”.
When all error (overrun,
framing, and parity) are
removed, the flag is cleared.
Set the serial I/O mode select
bits to ”000
2
”.
Set the receive enable bit to
“0”.
Read the lower-order byte of
the UARTi receive buffer
register.
Overrun error
Framing error
Parity error
Error-sum flag