參數(shù)資料
型號(hào): M30201M4T
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述: 單片16位CMOS微機(jī)
文件頁(yè)數(shù): 99/159頁(yè)
文件大?。?/td> 2319K
代理商: M30201M4T
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Unde
Programmable I/O Port
deeopmen
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
99
Programmable I/O Ports
There are 43 programmable I/O ports: P0 to P7. Each port can be set independently for input or output
using the direction register. A pull-up resistance for each block of 4 ports can be set. The port P1 allows the
drive capacity of its N-channel output transistor to be set as necessary.
Figures 1.90 to 1.92 show the programmable I/O ports.
Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices.
To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input
mode. When the pins are used as the outputs for the built-in peripheral devices, they function as outputs
regardless of the contents of the direction registers. See the descriptions of the respective functions for how
to set up the built-in peripheral devices.
(1) Direction registers
Figure 1.93 shows the direction registers.
These registers are used to choose the direction of the programmable I/O ports. Each bit in these regis-
ters corresponds one for one to each I/O pin.
(2) Port registers
Figure 1.94 shows the port registers.
These registers are used to write and read data for input and output to and from an external device. A
port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit
in port registers corresponds one for one to each I/O pin.
(3) Pull-up control registers
Figure 1.95 shows the pull-up control registers.
The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports
are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is
set for input.
(4) Port P1 drive capacity control register
Figure 1.95 shows a structure of the port P1 drive capacity control register.
This register is used to control the drive capacity of the port P1's N-channel output transistor. Each bit in
this register corresponds one for one to the port pins.
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