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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
221
(3) Frequency division ratio
In timer mode or pulse width modulation mode, [the value set in the timer register + 1] becomes the
frequency division ratio. In event counter mode, [the set value + 1] becomes the frequency division
ratio when a down count is performed, or [FFFF16 - the set value + 1] becomes the frequency division
ratio when an up count is performed. In one-shot timer mode, the value set in the timer register be-
comes the frequency division ratio.
The counter overflows (or underflows) when a count source equal to a frequency division ratio is input,
and an interrupt occurs. For the pulse output function, the output from the port varies (the value in the
port register does not vary).
(4) Reading the timer
Either in timer mode or in event counter mode, reading the timer register takes out the count at that
moment. Read it in 16-bit units. The data either in one-shot timer mode or in pulse width modulation
mode is indeterminate. In both the pulse period measurement mode and pulse width measurement
mode, an indeterminate value is read until the second effective edge is input after a count is started,
otherwise, the measurement results are read.
(5) Writing to the timer
When writing to the timer register while a count is in progress, the value is written only to the reload
register. When writing to the timer register while a count has stopped, the value is written both to the
reload register and the count. Write the value in 16-bit increments. The timer register cannot be
written to in either the pulse period measurement mode or the pulse width measurement mode.
(6) Relation between the input/output to/from the timer and the direction register
With the output function of the timer, set the direction register of the relevant port to input. To input an
external signal to the timer, set the direction register of the relevant port to input. However, pulse
output cannot be selected when inputting an external signal to the timer, and vice-versa.
(7) Pins related to timer X
(a) TX0INOUT, TX1INOUT, TX2INOUT
Input/output pins to timer X.
(8) Registers related to timer X
Figure 2.4.1 shows the memory map of timer X-related registers. Figures 2.4.2 and 2.4.3 show timer
X-related registers.
005616
005716
005816
038016
038116
038216
038316
038416
038816
038916
038A16
038B16
038C16
038D16
039716
039816
039916
Timer X0 (TX0)
Count start flag (TABSR)
One-shot start flag (ONSF)
Up-down flag (UDF)
Trigger select register (TRGSR)
Clock prescaler reset flag (CPSRF)
Timer X2 interrupt control register (TX2IC)
Timer X0 mode register (TX0MR)
Timer X0 interrupt control register (TX0IC)
Timer X1 interrupt control register (TX1IC)
Timer X1 (TX1)
Timer X2 (TX2)
Timer X1 mode register (TX1MR)
Timer X2 mode register (TX2MR)
Figure 2.4.1. Memory map of timer X-related registers