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參數(shù)資料
| 型號： | M30100M6T-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP32 |
| 封裝： | 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32 |
| 文件頁數(shù)： | 5/163頁 |
| 文件大?。?/td> | 1678K |
| 代理商： | M30100M6T-XXXFP |
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Serial I/O
Under
development
Tentative Specifications REV.E
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
102
Specification
Transfer data length: 8 bits
When internal clock is selected (bit 3 at address 00A016,00A816 = “0”) : fi/ 2(n+1) (Note 1)
fi = f1, f8, f32, fc
When external clock is selected (bit 3 at address 00A016,00A816 = “1”) : Input from CLKi pin
To start transmission, the following requirements must be met:
_ Transmit enable bit (bit 0 at address 00A516,00AD16) = “1”
_ Transmit buffer empty flag (bit 1 at addresses 00A516,00AD16) = “0”
Furthermore, if external clock is selected, the following requirements must also be met:
_ CLKi polarity select bit (bit 6 at address 00A416,00AC16) = “0”: CLKi input level = “H”
_ CLKi polarity select bit (bit 6 at address 00A416,00AC16) = “1”: CLKi input level = “L”
To start reception, the following requirements must be met:
_ Receive enable bit (bit 2 at address 00A516,00AD16) = “1”
_ Transmit enable bit (bit 0 at address 00A516,00AD16) = “1”
_ Transmit buffer empty flag (bit 1 at address 00A516,00AD16) = “0”
Furthermore, if external clock is selected, the following requirements must also be met:
_ CLKi polarity select bit (bit 6 at address 00A416,00AC16) = “0”: CLKi input level = “H”
_ CLKi polarity select bit (bit 6 at address 00A416,00AC16) = “1”: CLKi input level = “L”
When transmitting
_ Transmit interrupt cause select bit (bit 0 and bit 1 at address 00B016) = “0”: Inter-
rupts requested when data transfer from UARTi transfer buffer register to UARTi
transmit register is completed
_ Transmit interrupt cause select bit (bit 0 and bit 1 at address 00B016) = “1”: Inter-
rupts requested when data transmission from UARTi transfer register is completed
When receiving
_ Interrupts requested when data transfer from UARTi receive register to UARTi re-
ceive buffer register is completed
Overrun error (Note 2)
This error occurs when the next data is ready before contents of UARTi receive
buffer register are read out
CLK polarity selection
Whether transmit data is output/input at the rising edge or falling edge of the transfer
clock can be selected
LSB first/MSB first selection
Whether transmission/reception begins with bit 0 or bit 7 can be selected
Continuous receive mode selection
Reception is enabled simultaneously by a read from the receive buffer register
Transfer clock output from multiple pins selection
UART1 transfer clock can be chosen by software to be output from one of the two pins set
RxD1 input pin selection
UART1 RxD1 can be chosen by software to be input to one of the two pins set
Clock synchronous serial I/O mode
Item
Transfer data format
Transfer clock
Transmission start
condition
Reception start
conditio
Interrupt request
generation timing
Error detection
Select function
Table 1.15.1. Specifications of clock synchronous serial I/O mode
(1) Clock synchronous serial I/O mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. (See Table
1.15.1.) Figure 1.15.6 shows the UARTi transmit/receive mode register.
Note 1: “n” denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.
Note 2: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
the UARTi receive interrupt request bit does not change.
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