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參數(shù)資料
| 型號： | M30100M6T-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP32 |
| 封裝： | 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32 |
| 文件頁數(shù)： | 10/163頁 |
| 文件大?。?/td> | 1678K |
| 代理商： | M30100M6T-XXXFP |
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Under
development
Tentative Specifications REV.E
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
107
(2) Clock asynchronous serial I/O (UART) mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. (See Table 1.15.3.) Figure 1.15.11 shows the UARTi transmit/receive mode register.
Clock asynchronous serial I/O (UART) mode
Transfer data format
Transfer clock
Transmission start
condition
Reception start condi-
tion
Interrupt request gen-
eration timing
Error detection
Select function
Item
Specification
Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected
Start bit: 1 bit
Parity bit: Odd, even, or nothing as selected
Stop bit: 1 bit or 2 bits as selected
When internal clock is selected (bit 3 at addresses 00A016, 00A816 = “0”) :
fi/16(n+1) (Note 1) fi = f1, f8, f32, fC
When external clock is selected (bit 3 at addresses 00A016=“1”) :
fEXT/16(n+1) (Note 1) (Note 2)
To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 at addresses 00A516, 00AD16) = “1”
- Transmit buffer empty flag (bit 1 at addresses 00A516, 00AD16) = “0”
To start reception, the following requirements must be met:
- Receive enable bit (bit 2 at addresses 00A516, 00AD16) = “1”
- Start bit detection
When transmitting
- Transmit interrupt cause select bits (bits 0,1 at address 00B016) = “0”:
Interrupts requested when data transfer from UARTi transfer buffer register
to UARTi transmit register is completed
- Transmit interrupt cause select bits (bits 0, 1 at address 00B016) = “1”:
Interrupts requested when data transmission from UARTi transfer register is
completed
When receiving
- Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
Overrun error (Note 3)
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
Framing error
This error occurs when the number of stop bits set is not detected
Parity error
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is
encountered
RxD1 input pin selection
UART1 RxD1 can be chosen by software to be input to one of the two pins set
Table 1.15.3. Specifications of UART Mode
Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.
Note 2: fEXT is input from the CLKi pin.
Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
the UARTi receive interrupt request bit does not change.
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