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參數(shù)資料
| 型號(hào)： | M2V64S40DTP-8 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 64M Synchronous DRAM |
| 中文描述： | 6400同步DRAM |
| 文件頁數(shù)： | 4/52頁 |
| 文件大?。?/td> | 674K |
| 代理商： | M2V64S40DTP-8 |
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Apr. '99
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.2)
M2V64S20BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
4
PIN FUNCTION
CLK
Input
Master Clock: All other inputs are referenced to the rising edge of CLK.
CKE
Input
Clock Enable: CKE controls internal clock. When CKE is low, internal clock
for the following cycle is ceased. CKE is also used to select auto / self
refresh. After self refresh mode is started, CKE becomes asynchronous
input. Self refresh is maintained as long as CKE is low.
/CS
Input
Chip Select: When /CS is high, any command means No Operation.
/RAS, /CAS, /WE
Input
Combination of /RAS, /CAS, /WE defines basic commands.
A0-11
Input
A0-11 specify the Row / Column Address in conjunction with BA0,1. The
Row Address is specified by A0-11. The Column Address is specified by
A0-A9(x4), A0-A8(x8), A0-7(x16) . A10 is also used to indicate precharge
option. When A10 is high at a read / write command, an auto precharge
is performed. When A10 is high at a precharge command, all banks are
precharged.
BA0,1
Input
Bank Address: BA0,1 specifies one of four banks to which a command is
applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands.
DQ0-3(x4),
DQ0-7(x8),
DQ0-15(x16)
Input / Output
Data In and Data out are referenced to the rising edge of CLK.
DQM(x4,x8),
DQMU/L(x16)
Input
Din Mask / Output Disable: When DQMU/L is high in burst write, Din for the
current cycle is masked. When DQMU/L is high in burst read,
Dout is disabled at the next but one cycle.
Vdd, Vss
Power Supply
Power Supply for the memory array and peripheral circuitry.
VddQ, VssQ
Power Supply
VddQ and VssQ are supplied to the Output Buffers only.
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| M2V64S40DTP-8L | 64M Synchronous DRAM |
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| M2V64S40BTP | 64M bit Synchronous DRAM |
| M2V64S40BTP-10 | 64M bit Synchronous DRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M2V64S40DTP-8L | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M Synchronous DRAM |
| M2V64S40TP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M bit Synchronous DRAM |
| M2V64S4DTP-6 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M Synchronous DRAM |
| M2V64S4DTP-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M Synchronous DRAM |
| M2V64S4DTP-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M Synchronous DRAM |
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