參數(shù)資料
型號(hào): M2V64S30BTP-8L
廠商: Mitsubishi Electric Corporation
英文描述: 64M bit Synchronous DRAM
中文描述: 6400位同步DRAM
文件頁(yè)數(shù): 14/52頁(yè)
文件大?。?/td> 674K
代理商: M2V64S30BTP-8L
Apr. '99
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.2)
M2V64S20BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
14
[ /CAS LATENCY ]
/CAS latency, CL, is used to synchronize the first output data with the CLK frequency, i.e., the
speed of CLK determines which CL should be used. First output data is available after CL
cycles from READ command.
/CAS Latency Timing(BL=4)
CLK
Command
Address
X
ACT
READ
Y
tRCD
DQ
Q0
Q1
Q2
Q3
DQ
Q0
Q1
Q2
Q3
CL=2
CL=3
CL=2
CL=3
[ BURST LENGTH ]
The burst length, BL, determines the number of consecutive writes or reads that will be
automatically performed after the initial write or read command. For BL=1,2,4,8, full page the
output data is tristated (Hi-Z) after the last read. For BL=FP (Full Page), the TBST (Burst
Terminate) command should be issued to stop the output of data.
Burst Length Timing( CL=2 )
CLK
Command
Address
tRCD
DQ
Q0
BL=1
DQ
Q0
Q1
BL=2
DQ
Q0
Q1
Q2
Q3
BL=4
DQ
Q0
Q1
Q2
Q3
BL=8
Q4
Q5
Q6
Q7
ACT
READ
X
Y
DQ
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Qm
Q0
Q1
M2V64S20B : m=1023
M2V64S30B : m=511
M2V64S40B : m=255
Full Page counter rolls over
and continues to count.
BL=FP
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