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參數(shù)資料
| 型號(hào)： | M2V56S40TP-8 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 256M Synchronous DRAM |
| 中文描述： | 256M同步DRAM |
| 文件頁數(shù)： | 4/49頁 |
| 文件大?。?/td> | 244K |
| 代理商： | M2V56S40TP-8 |
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Feb.2000
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
256M Synchronous DRAM
4
PIN FUNCTION
CLK
Input
Master Clock: All other inputs are referenced to the rising edge of CLK.
CKE
Input
Clock Enable: CKE controls internal clock. When CKE is low, internal clock
for the following cycle is ceased. CKE is also used to select auto / self
refresh. After self refresh mode is started, CKE becomes asynchronous
input. Self refresh is maintained as long as CKE is low.
/CS
Input
Chip Select: When /CS is high, any command means No Operation.
/RAS, /CAS, /WE
Input
Combination of /RAS, /CAS, /WE defines basic commands.
A0-12
Input
A0-12 specify the Row / Column Address in conjunction with BA0,1. The
Row Address is specified by A0-12. The Column Address is specified by
A0-9,11. A10 is also used to indicate precharge option. When A10 is
high at a read / write command, an auto precharge is performed. When
A10 is high at a precharge command, all banks are precharged.
BA0,1
Input
DQ0-15
Input / Output
DQM
DQMU/L
Input
Vdd, Vss
Power Supply
Power Supply for the memory array and peripheral circuitry.
VddQ, VssQ
Power Supply
VddQ and VssQ are supplied to the Output Buffers only.
Bank Address: BA0,1 specifies one of four banks to which a command is
applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands.
Data In and Data out are referenced to the rising edge of CLK.
Din Mask / Output Disable: When DQMU/L is high in burst write, Din for
the current cycle is masked. When DQMU/L is high in burst read, Dout is
disabled at the next but one cycle.
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