參數(shù)資料
型號： M2V56D40ATP-75L
廠商： Mitsubishi Electric Corporation
英文描述： 256M Double Data Rate Synchronous DRAM
中文描述： 256M雙數(shù)據(jù)速率同步DRAM
文件頁數(shù)： 19/40頁
文件大?。?/td> 768K
代理商： M2V56D40ATP-75L
19
MITSUBISHI ELECTRIC
Mar. '02
MITSUBISHI LSIs
DDR SDRAM
(Rev.1.44)
M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10
M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10
256M Double Data Rate Synchronous DRAM
-75A / -75
-10
x4
95
85
x8
100
90
x16
115
105
x4
140
100
x8
150
115
x16
180
145
x4
130
95
x8
140
105
x16
160
120
IDD5
AUTO REFRESH CURRENT: t RC = t RFC (MIN)
ALL
140
130
ALL(-75A/-75/-10)
3
3
9
ALL(-75AL/-75A/-10L)
2
2
9,21
x4
215
170
20
x8
235
185
20
x16
270
210
20
IDD6
SELF REFRESH CURRENT: CKE < 0.2V
6
6
ALL
IDD4W
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank
active; Address and control inputs changing once per clock cycle;
CL=2.5; t CK = t CK MIN;DQ, DM and DQS inputs changing twice per
clock cycle
ALL
ALL
IDD3Ppower-down mode; CKE < VIL (MAX); t CK = t CK MIN
ACTIVE STANDBY CURRENT: /CS > VIH (MIN); CKE > VIH (MIN); One
bank; Active-Precharge; t RC = t RAS MAX; t CK = t CK MIN; DQ,DM
and DQS inputs changing twice per clock cycle; address and other
control inputs changing once per clock cycle
IDD3N
ALL
45
IDD7
OPERATING CURRENT-Four bank Operation: Four bank are interleaved
with BL=4, refer to the Notes 20
35
IDD4R
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;One bank
active; Address and control inputs changing once per clock cycle;CL=2.5;
t CK = t CK MIN; IOUT = 0 mA
mA
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;
power-down mode; CKE <VIL (MAX); t CK = t CK MIN
25
30
15
12
Organization
Parameter/Test Conditions
OPERATING CURRENT: One Bank; Active-Precharge; t RC = t RC MIN;
t CK = t CK MIN; DQ, DM and DQS inputs changing twice per clock
cycle; address and control inputs changing once per clock cycle
Unit
Limits(Max.)
ALL
85
75
IDD2P
IDD2F
IDLE STANDBY CURRENT: /CS > VIH (MIN); All banks idle;
CKE > VIH (MIN); t CK = t CK MIN; Address and other control inputs
changing once per clock cycle
Notes
IDD0
IDD1
OPERATING CURRENT: One Bank; Active-Read-Precharge;
Burst = 2; t RC = t RC MIN; CL = 2.5; t CK = t CK MIN; IOUT= 0mA;
Address and control inputs changing once per clock cycle
Symbol
AVERAGE SUPPLY CURRENT from VDD
(Ta=0 ~ 70
o
C, VDD = VDDQ = 2.5V + 0.2V, VSS = VSSQ = 0V, Output Open, unless otherwise noted)
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70
o
C, VDD = VDDQ = 2.5V + 0.2V, VSS = VSSQ = 0V, Output Open, unless otherwise noted)
Min.
Max.
VIH(AC) High-Level Input Voltage (AC)
VIL(AC) Low-Level Input Voltage (AC)
VID(AC) Input Differential Voltage, CLK and /CLK
VIX(AC) Input Crossing Point Voltage, CLK and /CLK
IOZ
Off-state Output Current /Q floating Vo=0~VddQ
II
Input Current / VIN=0 ~ VddQ
IOH
Output High Current (VOUT = VTT+0.84V)
IOL
Output High Current (VOUT = VTT-0.84V)
VREF + 0.31
VREF - 0.31
VDDQ + 0.6
0.7
7
8
0.5*VDDQ - 0.2 0.5*VddQ + 0.2
-5
-2
-16.8
16.8
5
2
Symbol
Parameter / Test Conditions
Unit
V
V
V
V
mA
mA
Notes
Limits
mA
mA
相關PDF資料
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