- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370828 > M2V56D40ATP-75 (Mitsubishi Electric Corporation) 256M Double Data Rate Synchronous DRAM PDF資料下載
參數(shù)資料
| 型號(hào)： | M2V56D40ATP-75 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 256M Double Data Rate Synchronous DRAM |
| 中文描述： | 256M雙數(shù)據(jù)速率同步DRAM |
| 文件頁數(shù)： | 34/40頁 |
| 文件大?。?/td> | 768K |
| 代理商： | M2V56D40ATP-75 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁當(dāng)前第34頁第35頁第36頁第37頁第38頁第39頁第40頁
34
MITSUBISHI ELECTRIC
Mar. '02
MITSUBISHI LSIs
DDR SDRAM
(Rev.1.44)
M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10
M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10
256M Double Data Rate Synchronous DRAM
Burst write operation can be interrupted by Write to any bank. Random column access is allowed. WRITE
to WRITE interval is 1 CLK minimum.
[Write interrupted by Write]
[Write interrupted by Read]
Burst write operation can be interrupted by read of the same or the other bank. Random column access is
allowed. Internal WRITE to READ command interval(tWTR) is 1 CLK minimum. The input data masked by
DM in the interrupted READ cycle is "don't care". tWTR is referenced from the first positive edge after the last
data input.
Write Interrupted by Read (BL=8, CL=2.5)
Command
A0-9,11
A10
BA0,1
DQ
WRITE
Yi
0
00
READ
Yj
0
00
Dai0
Dai1
Qaj0
Qaj1 Qaj2 Qaj3
QS
Qaj4 Qaj5 Qaj6
Qaj7
DM
tWTR
/CLK
CLK
Write Interrupted by Write (BL=8)
Command
A0-9,11
A10
BA0,1
WRITE
Yi
0
00
WRITE
Yk
0
10
WRITE
Yj
0
00
WRITE
Yl
0
00
DQ
Dai1
Daj1
Daj3
Dak1
Dak3
Dak5
Dal1
DQS
Dal2 Dal3
Dal5 Dal6
Dal7
Dal4
Dal0
Dak4
Dak2
Dak0
Dai0
Daj0
Daj2
/CLK
CLK
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M2V56D40ATP-75A | 256M Double Data Rate Synchronous DRAM |
| M2V56D40ATP-75AL | 256M Double Data Rate Synchronous DRAM |
| M2V56D40ATP-75L | 256M Double Data Rate Synchronous DRAM |
| M2V56D40ATP75A | 256M Double Data Rate Synchronous DRAM |
| M2S56D20ATP-10L | 256M Double Data Rate Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M2V56D40ATP75A | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM |
| M2V56D40ATP-75A | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM |
| M2V56D40ATP-75AL | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM |
| M2V56D40ATP-75L | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM |
| M2V56S20AKT | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Synchronous DRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。