參數(shù)資料
型號: M2V56D40AKT-10L
廠商: Mitsubishi Electric Corporation
英文描述: JT 6C 6#22D SKT PLUG
中文描述: 256M雙數(shù)據(jù)速率同步DRAM
文件頁數(shù): 25/40頁
文件大?。?/td> 768K
代理商: M2V56D40AKT-10L
25
MITSUBISHI ELECTRIC
Mar. '02
MITSUBISHI LSIs
DDR SDRAM
(Rev.1.44)
M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10
M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10
256M Double Data Rate Synchronous DRAM
The DDR SDRAM has four independent banks. Each bank is activated by the ACT command with the bank
addresses (BA0,1). A row is indicated by the row address A12-0. The minimum activation interval between
banks is tRRD.
BANK ACTIVATE (ACT)
OPERATIONAL DESCRIPTION
The PRE command deactivates the bank indicated by BA0,1. When multiple banks are active, the precharge
all command (PREA,PRE+A10=H) is available to deactivate all banks at the same time. After tRP from the
precharge, an ACT command to the same bank can be issued.
PRECHARGE (PRE)
Bank Activation and Precharge All (BL=8, CL=2)
A precharge command can be issued after BL/2 time from a read command.
Precharge all
Command
A0-9,11
A10
BA0,1
DQ
ACT
Xa
Xa
00
READ
Y
0
00
ACT
Xb
Xb
01
PRE
tRRD
tRCD
1
ACT
Xb
Xb
01
tRAS
tRP
tRCmin
2 ACT command / tRCmin
DQS
Qa0
BL/2
Qa1
Qa2
Qa3
Qa4
Qa5
Qa6
Qa7
/CLK
CLK
相關(guān)PDF資料
PDF描述
M2S56D40AKT-10L JT 4C 4#22 SKT PLUG
M2V56D20AKT-75 256M Double Data Rate Synchronous DRAM
M2S56D20AKT-75 256M Double Data Rate Synchronous DRAM
M2V56D30AKT-75 JT 13C 13#22D SKT GRND PLUG
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M2V56D40AKT-75 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM
M2V56D40AKT-75A 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM
M2V56D40AKT-75AL 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM
M2V56D40AKT-75L 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM
M2V56D40ATP-10 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM