參數(shù)資料
型號: M2V12D30TP
廠商: Mitsubishi Electric Corporation
英文描述: 512M Double Data Rate Synchronous DRAM
中文描述: 512M雙數(shù)據(jù)速率同步DRAM
文件頁數(shù): 4/38頁
文件大?。?/td> 754K
代理商: M2V12D30TP
MITSUBISHI
ELECTRIC
-4-
M2S12D20/ 30TP -75, -75L, -10, -10L
512M Double Data Rate Synchronous DRAM
Feb. '02
MITSUBISHI LSIs
DDR SDRAM (Rev.1.1)
MITSUBISHI ELECTRIC
Type Designation Code
This rule is applied to only Synchronous DRAM family.
Mitsubishi Main Designation
Speed Grade 10: 125MHz@CL=2.5,100MHz@CL=2.0
75:
133MHz@CL=2.5
,100MHz@CL=2.0
Package Type TP: TSOP(II)
Process Generation (blank):1st gen.
Function Reserved for Future Use
Organization 2n
2: x4, 3: x8
DDR Synchronous DRAM
Density 12: 512M bits
Interface V:LVTTL, S:SSTL_3, _2
Memory Style (DRAM)
M 2 S 12 D 3 0 TP –75 L
BLOCK DIAGRAM
/CS /RAS /CAS
/WE
DM
Memory
Array
Bank #0
DQ0 - 7
I/O Buffer
Memory
Array
Bank #1
Memory
Array
Bank #2
Memory
Array
Bank #3
Mode Register
Control Circuitry
Address Buffer
A0-12
BA0,1
Clock Buffer
CLK
CKE
Control Signal Buffer
QS Buffer
DQS
DLL
/CLK
Power Grade L:Low power, (blank):standard
相關(guān)PDF資料
PDF描述
M2V12D30TP-75L 512M Double Data Rate Synchronous DRAM
M2S12D20TP-75L 512M Double Data Rate Synchronous DRAM
M2S12D30TP 512M Double Data Rate Synchronous DRAM
M2S12D30TP-75L 512M Double Data Rate Synchronous DRAM
M2S12D20TP-75 128 x 64 pixel format, LED Backlight available
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