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參數(shù)資料
| 型號(hào)： | M2S56D40ATP-75A |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 256M Double Data Rate Synchronous DRAM |
| 中文描述： | 256M雙數(shù)據(jù)速率同步DRAM |
| 文件頁數(shù)： | 22/40頁 |
| 文件大?。?/td> | 768K |
| 代理商： | M2S56D40ATP-75A |
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22
MITSUBISHI ELECTRIC
Mar. '02
MITSUBISHI LSIs
DDR SDRAM
(Rev.1.44)
M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10
M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10
256M Double Data Rate Synchronous DRAM
Note:
1. All voltages are referenced to VSS.
2. Tests for AC timing, IDD, and electrical AC and DC characteristics, may be conducted at nominal
reference/supply voltage levels. However, the specifications and device operations are guaranteed for the full
voltage range specified.
3. AC timing and IDD tests may use the VIL to VIH swing of up to 1.5V in the test environment. Input timing is
still referenced to VREF (or to the crossing point for CK//CK), and parameter specifications are guaranteed
for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is
1V/ns in the range between VIL(AC) and VIH(AC).
4. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver will
effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as
the signal does not ring back above (below) the DC input LOW (HIGH) level.
5. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the DC level
of the same. Peak-to-peak noise on VREF may not exceed +2% of the DC value.
6. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected
to be set equal to VREF, and must track variations in the DC level of VREF.
7. VID is the magnitude of the difference between the input level on CLK and the input level on /CLK.
8. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the
DC
level of the same.
9. Enables on-chip refresh and address counters.
10. IDD specifications are tested after the device is properly initialized.
11. This parameter is sampled. VDDQ = 2.5V+0.2V, VDD = 2.5V + 0.2V , f = 100 MHz, Ta = 25
o
C, VOUT(DC) =
VDDQ/2, VOUT(PEAK TO PEAK) = 25mV. DM inputs are grouped with I/O pins - reflecting the fact that
they are matched in loading (to facilitate trace matching at the board level).
12. The CLK//CLK input reference level (for timing referenced to CLK//CLK) is the point at which CLK and /CLK
cross; the input reference level for signals other than CLK//CLK, is VREF.
13. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes,
CKE< 0.3VDDQ is recognized as LOW.
14. t HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters
are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ),
or begins driving (LZ).
15. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for
this parameter, but system performance (bus turnaround) will degrade accordingly.
16. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or
before this CLK edge. A valid transition is defined as monotonic, and satisfies the input slew rate
specifications. When no writes were previously in progress on the bus, DQS will be transitioning from
High-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
HIGH to LOW at this time, depending on tDQSS.
17. A maximum of eight AUTO REFRESH commands can be asserted to any given DDR SDRAM device.
18. tXPRD should be 200 tCLK when the clocks are unstable during the power down mode.
19. For command/address and CK & /CK slew rate > 1.0V/ns.
(Notes continued on next page)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M2S56D40ATP-75AL | 256M Double Data Rate Synchronous DRAM |
| M2S56D40ATP-75L | 256M Double Data Rate Synchronous DRAM |
| M2S56D40ATP75A | 256M Double Data Rate Synchronous DRAM |
| M2V56D30AKT-10L | Circular Connector; No. of Contacts:100; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:22; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:22-35 RoHS Compliant: No |
| M2S56D30AKT-10L | Circular Connector; No. of Contacts:3; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:8; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:8-98 RoHS Compliant: No |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M2S56D40ATP-75AL | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM |
| M2S56D40ATP-75L | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM |
| M-2-SA | 制造商:Excelta Corporation 功能描述:THREE STAR MINITURE TWEEZER 3-1/2 " 制造商:Excelta Corporation 功能描述:THREE STAR MINITURE TWEEZER, 3-1/2 "; Tweezer Type:Straight; Overall Length:3.5"; Tweezer Body Material:Stainless Steel; Tweezer Tip Material:Stainless Steel ;RoHS Compliant: NA |
| M2SA5802 | 制造商:Omron Electronic Components LLC 功能描述:RED SCREEN - Bulk 制造商:Omron Electronic Components LLC 功能描述:HEAVY DUTY SWITCHES RED SCREEN |
| M2SA-5802 | 功能描述:RED SCREEN RoHS:是 類別:未定義的類別 >> 其它 系列:* 標(biāo)準(zhǔn)包裝:1 系列:* 其它名稱:MS305720A |
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