參數(shù)資料
型號(hào)： M2S56D30AKT-75L
廠商： Mitsubishi Electric Corporation
英文描述： 256M Double Data Rate Synchronous DRAM
中文描述： 256M雙數(shù)據(jù)速率同步DRAM
文件頁數(shù)： 40/40頁
文件大?。?/td> 768K
代理商： M2S56D30AKT-75L
40
MITSUBISHI ELECTRIC
Mar. '02
MITSUBISHI LSIs
DDR SDRAM
(Rev.1.44)
M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10
M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10
256M Double Data Rate Synchronous DRAM
Revision History
- Add Low power version Spec.
- Overshoot / Undershoot Spec Add
Mar.’02
1.44
-Unify *ATP’s spec. with *AKT’s spec. (Add *AKT spec to *ATP spec.)
-Change page 37 (Fig. : Self Refresh)
-Change IDD7 measurement timing (page 23:Note 20)
-Modify Average Supply Current from VDD
-75A / -75 /-10 -75A & -75 / -10
IDD0 X4 Limits (from 105 / 105 / 120mA to 85 / 75mA)
IDD0 X8 Limits (from 110 / 110 / 120mA to 85 / 75mA)
IDD0 X16 Limits (from 120 / 120 / 115mA to 85 / 75mA)
IDD1 X4 Limits (from 110 / 110 / 105mA to 95 / 85mA)
IDD1 X8 Limits (from 115 / 115 / 110mA to 100 / 90mA)
IDD1 X16 Limits (from 135 / 135 / 130mA to 115 / 105mA)
IDD2P Limits (from 20 / 20 / 20mA to 6 / 6mA)
IDD2F Limits (from 40 / 40 / 40mA to 30 / 25mA)
IDD3P Limits (from 30 / 30 / 30mA to 15 / 12mA)
IDD3N X4 Limits (from 60 / 60 / 55mA to 45 / 35mA)
IDD3N X8 Limits (from 65 / 65 / 60mA to 45 / 35mA)
IDD3N X16 Limits (from 75 / 75 / 70mA to 45 / 35mA)
IDD4R X4 Limits (from 150 / 150 / 140mA to 140 / 100mA)
IDD4R X8 Limits (from 170 / 170 / 160mA to 150 / 115mA)
IDD4R X16 Limits (from 210 / 210 / 200mA to 180 / 145mA)
IDD4W X4 Limits (from 145 / 145 / 135mA to 130 / 95mA)
IDD4W X8 Limits (from 165 / 165 / 155mA to 140 / 105mA)
IDD4W X16 Limits (from 200 / 200 / 180mA to 160 / 120mA)
IDD5 Limits (from 185 / 185 / 175mA to 140 / 130mA)
IDD7 X4 Limits (from 250 / 250 / 230mA to 215 / 170mA)
IDD7 X8 Limits (from 260 / 260 / 240mA to 235 / 185mA)
IDD7 X16 Limits (from 290 / 290 / 280mA to 270 / 210mA)
Jan.‘02
1.33
-Added Operating description Table when new command asserted while write &
read with auto precharge is issued.
Jun.’01
1.2
Jun.’01
May ’01
Date
-Added -75A Spec.
-Added IDD7 Spec.
-Changed VIH(DC)min Spec. from VREF+0.18V to VREF+0.15V
-Changed VIL(DC)min Spec. from VREF-0.18V to VREF-0.15V
-Changed VIH(AC)min Spec. from VREF+0.35V to VREF+0.31V
-Changed VIL(AC)max Spec. from VREF-0.35V to VREF-0.31V
-Changed IOH Spec. from -15.2mA to -16.8mA
-Changed IOL Spec. from +15.2mA to +16.8mA
1.1
-New registration (May. ‘01)
1.02
Description
Rev.
相關(guān)PDF資料
PDF描述
M2S56D30ATP 256M Double Data Rate Synchronous DRAM
M2S56D40ATP-75A 256M Double Data Rate Synchronous DRAM
M2S56D40ATP-75AL 256M Double Data Rate Synchronous DRAM
M2S56D40ATP-75L 256M Double Data Rate Synchronous DRAM
M2S56D40ATP75A 256M Double Data Rate Synchronous DRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M2S56D30ATP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM
M2S56D30ATP-10 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM
M2S56D30ATP-10L 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM
M2S56D30ATP-75 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM
M2S56D30ATP75A 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM
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