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參數(shù)資料
| 型號： | M2S56D20ATP75A |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 256M Double Data Rate Synchronous DRAM |
| 中文描述： | 256M雙數(shù)據(jù)速率同步DRAM |
| 文件頁數(shù)： | 15/40頁 |
| 文件大小： | 768K |
| 代理商： | M2S56D20ATP75A |
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15
MITSUBISHI ELECTRIC
Mar. '02
MITSUBISHI LSIs
DDR SDRAM
(Rev.1.44)
M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10
M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10
256M Double Data Rate Synchronous DRAM
POWER ON SEQUENCE
The following power on sequences are necessary to guarantee the proper operations of the
DDR SDRAM.
1. Apply VDD before or at the same time as VDDQ
2. Apply VDDQ before or at the same time as VTT & VREF
3. Maintain stable conditions for 200us after stable power and CLK are applied, assert NOP or DSEL
4. Issue Precharge command for all banks of the device
5. Issue EMRS to program proper functions
6. Issue MRS to configure the Mode Register and to reset the DLL
7. Issue 2 or more Auto Refresh commands
8. Maintain stable conditions for 200 cycle
After these sequences, the DDR SDRAM is in the idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by
configuring the mode register (MRS). The mode register stores these data
until the next MRS command, which may be issued when both banks are in
idle state. After tMRD from an MRS command, the DDR SDRAM is ready to
accept the new command.
/CS
/RAS
/CAS
/WE
A11-A0
/CLK
CLK
BA0
BA1
R: Reserved for Future Use
0
1
NO
YES
DLL Reset
0
1
Sequential
Interleaved
Burst Type
BT=0
R
2
4
8
R
R
R
R
BT=1
R
2
4
8
R
R
R
R
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
BL
Burst
Length
/CAS Latency
R
R
2
R
R
R
2.5
R
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
CL
Latency
Mode
BA1 BA0 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
0
0
DR
0
BT
LTMODE
BL
V
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| M2S56D30AKT | 256M Double Data Rate Synchronous DRAM |
| M2S56D30AKT-75A | 256M Double Data Rate Synchronous DRAM |
| M2S56D30AKT-75AL | 256M Double Data Rate Synchronous DRAM |
| M2S56D30AKT-75L | 256M Double Data Rate Synchronous DRAM |
| M2S56D30ATP | 256M Double Data Rate Synchronous DRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M2S56D20ATP-75A | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM |
| M2S56D20ATP-75AL | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM |
| M2S56D20ATP-75L | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM |
| M2S56D20TP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM |
| M2S56D20TP-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM |
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