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參數(shù)資料
| 型號： | M2S12D30TP-75L |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 512M Double Data Rate Synchronous DRAM |
| 中文描述： | 512M雙數(shù)據(jù)速率同步DRAM |
| 文件頁數(shù)： | 23/38頁 |
| 文件大?。?/td> | 754K |
| 代理商： | M2S12D30TP-75L |
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MITSUBISHI
ELECTRIC
-23-
M2S12D20/ 30TP -75, -75L, -10, -10L
512M Double Data Rate Synchronous DRAM
Feb. '02
MITSUBISHI LSIs
DDR SDRAM (Rev.1.1)
MITSUBISHI ELECTRIC
The DDR SDRAM has four independent banks. Each bank is activated by the ACT command with
the bank addresses (BA0,1). A row is indicated by the row address A12-0. The minimum activation
interval between banks is tRRD.
BANK ACTIVATE (ACT)
OPERATIONAL DESCRIPTION
The PRE command deactivates the bank indicated by BA0,1. When multiple banks are active, the
precharge all command (PREA,PRE+A10=H) is available to deactivate all banks them at the same time.
After tRP from the precharge, an ACT command to the same bank can be issued.
PRECHARGE (PRE)
Bank Activation and Precharge All (BL=8, CL=2)
A precharge command can be issued after BL/2 time from a read command.
Precharge all
Command
A0-9,11-12
A10
BA0,1
DQ
ACT
Xa
Xa
00
READ
Y
0
00
ACT
Xb
Xb
01
PRE
tRRD
tRCD
1
ACT
Xb
Xb
01
tRAS
tRP
tRCmin
2 ACT command / tRCmin
DQS
Qa0
BL/2
Qa1
Qa2
Qa3
Qa4
Qa5
Qa6
Qa7
/CLK
CLK
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M2S12D20TP-75 | 128 x 64 pixel format, LED Backlight available |
| M2V12D20TP-75 | 128 x 64 pixel format, LED Backlight available |
| M2S12D30TP-75 | 128 x 64 pixel format, LED Backlight available |
| M2V12D30TP-75 | 128 x 64 pixel format, LED Backlight available |
| M2V28D20ATP-75 | 128M Double Data Rate Synchronous DRAM |
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