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參數(shù)資料
| 型號： | M2S12D20TP-75L |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 512M Double Data Rate Synchronous DRAM |
| 中文描述： | 512M雙數(shù)據(jù)速率同步DRAM |
| 文件頁數(shù)： | 11/38頁 |
| 文件大?。?/td> | 754K |
| 代理商： | M2S12D20TP-75L |
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MITSUBISHI
ELECTRIC
-11-
M2S12D20/ 30TP -75, -75L, -10, -10L
512M Double Data Rate Synchronous DRAM
Feb. '02
MITSUBISHI LSIs
DDR SDRAM (Rev.1.1)
MITSUBISHI ELECTRIC
FUNCTION TRUTH TABLE for CKE
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
NOTES:
1. Low to High transition of CKE re-enable CLK and other inputs asynchronously.
A minimum setup time must be satisfied before any command except EXIT.
2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.
3. Must be legal command.
Current State
CKE n-1
CKE n
/CS
/RAS
/CAS
/WE
Address
Action
Notes
H
X
X
X
X
X
X
INVALID
1
L
H
H
X
X
X
X
Exit Self-Refresh (Idle after tRC)
1
L
H
L
H
H
H
X
Exit Self-Refresh (Idle after tRC)
1
L
H
L
H
H
L
X
ILLEGAL
1
L
H
L
H
L
X
X
ILLEGAL
1
L
H
L
L
X
X
X
ILLEGAL
1
L
L
X
X
X
X
X
NOP (Maintain Self-Refresh)
1
H
X
X
X
X
X
X
INVALID
L
H
X
X
X
X
X
Exit Power Down to Idle
L
L
X
X
X
X
X
NOP (Maintain Self-Refresh)
H
H
X
X
X
X
X
Refer to Function Truth Table
2
H
L
L
L
L
H
X
Enter Self-Refresh
2
H
L
H
X
X
X
X
Enter Power Down
2
H
L
L
H
H
H
X
Enter Power Down
2
H
L
L
H
H
L
X
ILLEGAL
2
H
L
L
H
L
X
X
ILLEGAL
2
H
L
L
L
X
X
X
ILLEGAL
2
L
X
X
X
X
X
X
Refer to Current State =Power Down
2
H
H
X
X
X
X
X
Refer to Function Truth Table
H
L
X
X
X
X
X
Begin CLK Suspend at Next Cycle
3
L
H
X
X
X
X
X
Exit CLK Suspend at Next Cycle
3
L
L
X
X
X
X
X
Maintain CLK Suspend
ANY STATE
other than listed
above
SELF-
REFRESHING
POWER
DOWN
ALL BANKS
IDLE
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| M2S12D30TP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:512M Double Data Rate Synchronous DRAM |
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| M2S12D30TP-75L | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:512M Double Data Rate Synchronous DRAM |
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