參數(shù)資料
型號： M29W040-200NZ6R
廠商： 意法半導(dǎo)體
英文描述： 4 Mbit 512Kb x8, Uniform Block Low Voltage Single Supply Flash Memory
中文描述： 4兆位512KB的× 8，統(tǒng)一座低電壓單電源閃存
文件頁數(shù)： 13/31頁
文件大?。?/td> 205K
代理商： M29W040-200NZ6R
Symbol
Alt
Parameter
M29W040
Unit
-100
-120
V
CC
= 3.3V
±
0.3V
C
L
= 30pF
V
CC
= 3.3V
±
0.3V
Min
Max
Min
Max
t
AVAV
t
WC
Address Valid to Next Address Valid
100
120
ns
t
ELWL
t
CS
Chip Enable Low to Write Enable Low
0
0
ns
t
WLWH
t
WP
Write Enable Low to Write Enable High
45
50
ns
t
DVWH
t
DS
Input Valid to Write Enable High
45
50
ns
t
WHDX
t
DH
Write Enable High to Input Transition
0
0
ns
t
WHEH
t
CH
Write Enable High to Chip Enable High
0
0
ns
t
WHWL
t
WPH
Write Enable High to Write Enable Low
25
30
ns
t
AVWL
t
AS
Address Valid to Write Enable Low
0
0
ns
t
WLAX
t
AH
WriteEnable Low to Address Transition
45
50
ns
t
GHWL
Output Enable High to Write Enable Low
0
0
ns
t
VCHEL
t
VCS
V
CC
High to Chip Enable Low
50
50
μ
s
t
WHQV1(1)
Write Enable High to Output Valid (Program)
12
12
μ
s
t
WHQV2(1)
Write Enable High to Output Valid
(Block Erase)
1.5
30
1.5
30
sec
t
WHGL
t
OEH
Write Enable High to Output Enable Low
0
0
ns
Note:
1. Time is measured to Data Polling or ToggleBit, t
WHQV
= t
WHQ7V
+ t
Q7VQV
.
Table13A. Write AC Characteristics,WriteEnable Controlled
(T
A
= 0 to 70
°
C, –20 to 85
°
C or –40 to 85
°
C)
ChipErase(CE)instruction.
Thisinstructionuses
six write cycles. The Erase Set-up command 80h
is written to address5555h on thirdcycleafter the
two coded cycles. The Chip Erase Confirm com-
mand10hiswrittenat address5555honsixthcycle
after anothertwo codedcycles.If the secondcom-
mand given is not an eraseconfirm or if thecoded
cycles are wrong, the instruction aborts and the
device is reset to ReadArray.It isnot necessaryto
program the array with 00h first as the P/E.C. will
automaticallydo this before erasing to FFh. Read
operations after the sixth rising edge of W or E
output the status register bits. During the execu-
tion of the erase bythe P/E.C.the memorywill not
acceptany instruction.
Readof DataPolling bit DQ7returns’0’, then’1’on
completion. The Toggle Bit DQ6 toggles during
erase operation and stops when erase is com-
pleted. After completion the Status Register bit
DQ5 returns ’1’ if there has been an Erase Failure
because the erasure has not been verified even
after the maximum number of erase cycles have
been executed.
13/31
M29W040
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