參數(shù)資料
型號: M29W040-200NZ1R
廠商: 意法半導(dǎo)體
英文描述: 4 Mbit 512Kb x8, Uniform Block Low Voltage Single Supply Flash Memory
中文描述: 4兆位512KB的× 8,統(tǒng)一座低電壓單電源閃存
文件頁數(shù): 6/31頁
文件大小: 205K
代理商: M29W040-200NZ1R
MemoryBlocks
The memoryblocksof the M29W040are shownin
Figure3. Thememory arrayis dividedin 8 uniform
blocks of 64 Kbytes. Each block can be erased
separately or any combination of blocks can be
erased simultaneously.The BlockErase operation
is managedautomaticallyby theP/E.C.Theopera-
tion can be suspended in order to read from any
other block, and thenresumed.
Block Protectionprovides additionaldata security.
Each uniformblockcan beseparatelyprotectedor
unprotectedagainstProgramorErase.BringingA9
and G to V
ID
initiatesprotection,whilebringingA9,
G and E to V
ID
cancels the protection. The block
affected during protection is addressed by the in-
puts on A16, A17, and A18. Unprotect operation
affectsall blocks.
Operations
Operations are defined as specific bus cycles and
signals which allow Memory Read, Command
Write, Output Disable, Standby,Read Status Bits,
Block Protect/Unprotect, Block Protection Check
and ElectronicSignatureRead. Theyare shownin
Tables 3, 4, 5.
Read.
Read operations are used to output the
contents of theMemory Array,the StatusRegister
or the Electronic Signature. Both Chip Enable E
and OutputEnable G must be low in order to read
the output of the memory. The Chip Enable input
alsoprovidespowercontroland shouldbe usedfor
deviceselection.OutputEnable shouldbe usedto
gatedataontotheoutputindependentof thedevice
selection.The data read dependson the previous
commandwritten to the memory (seeinstructions
RST and RSIG, and StatusBits).
Write.
WriteoperationsareusedtogiveInstruction
Commandsto the memory or to latchinput datato
be programmed.Awrite operationis initiatedwhen
Chip Enable E is Low and Write Enable W is Low
with OutputEnableG High.Addressesare latched
on thefallingedge of WorEwhicheveroccurslast.
CommandsandInputDataarelatchedon therising
edge of W or E whicheveroccursfirst.
OutputDisable.
Thedataoutputsare highimped-
ance when the OutputEnable G is High withWrite
Enable W High.
Standby.
The memory is in standby when Chip
Enable E is High and Program/Erase Controller
P/E.C. is Idle. The power consumptionis reduced
to the standby level and the outputs are high im-
pedance, independent of the Output Enable G or
WriteEnable W inputs.
Automatic Standby.
After150ns of inactivity and
when CMOS levels are driving the addresses,the
chip automaticallyenters a pseudo standby mode
where consumption is reduced to the CMOS
standby value, while outputs are still driving the
bus.
Power Down.
When the PD command is written
to the P/E.C. the memory enters a power down
statuswhere the power consumptionis reducedto
I
CC6
(typicallyless than 1.0
μ
A).
Electronic Signature.
Two codes identifying the
manufacturer andthedevicecanbe read fromthe
memory,themanufacturer’scodeforSTMicroelec-
tronics is 20h, and the device code is E3h for the
M29W040. These codes allow programming
equipment or applicationsto automatically match
theirinterfaceto thecharacteristicsof theparticular
manufacturer’s product. TheElectronicSignature
is output by a Read operation when the voltage
applied to A9 is at V
ID
and address inputs A1 and
A6 are at Low. The manufacturer code is output
when the Address input A0 is Low and the device
codewhen thisinputis High.OtherAddressinputs
are ignored. The codes are output on DQ0-DQ7.
This is shown in Table4.
The ElectronicSignaturecan alsobe read, without
raisingA9 to V
ID
by givingthe memorythe instruc-
tion RSIG (see below).
6/31
M29W040
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