參數(shù)資料
型號(hào)： M29W040-150NZ6TR
廠商： 意法半導(dǎo)體
英文描述： 4 Mbit 512Kb x8, Uniform Block Low Voltage Single Supply Flash Memory
中文描述： 4兆位512KB的× 8，統(tǒng)一座低電壓?jiǎn)坞娫撮W存
文件頁(yè)數(shù)： 10/31頁(yè)
文件大小： 205K
代理商： M29W040-150NZ6TR
Symbol
Alt
Parameter
Test Condition
M29W040
Unit
-100
-120
V
CC
= 3.3V
±
0.3V
C
L
= 30pF
V
CC
= 3.3V
±
0.3V
Min
Max
Min
Max
t
AVAV
t
RC
Address Valid to Next Address Valid
E = V
IL
, G = V
IL
100
120
ns
t
AVQV
t
ACC
Address Valid to Output Valid
E = V
IL
, G = V
IL
100
120
ns
t
ELQX
(1)
t
LZ
Chip Enable Low to Output Transition
G = V
IL
0
0
ns
t
ELQV
(2)
t
CE
Chip Enable Low to Output Valid
G = V
IL
100
120
ns
t
GLQX(1)
t
OLZ
Output Enable Low to Output
Transition
E = V
IL
0
0
ns
t
GLQV(2)
t
OE
Output Enable Low to Output Valid
E = V
IL
40
50
ns
t
EHQX
t
OH
Chip Enable High to Output
Transition
G = V
IL
0
0
ns
t
EHQZ(1)
t
HZ
Chip Enable High to Output Hi-Z
G = V
IL
20
30
ns
t
GHQX
t
OH
Output Enable High to Output
Transition
E = V
IL
0
0
ns
t
GHQZ(1)
t
DF
Output Enable High to Output Hi-Z
E = V
IL
20
30
ns
t
AXQX
t
OH
Address Transition to Output
Transition
E = V
IL
, G = V
IL
0
0
ns
Notes:
1. Sampled only, not 100% tested.
2. G may be delayed by up to t
ELQV
- t
GLQV
afterthe falling edge of E without increasing t
ELQV
.
Table12A. Read AC Characteristics
(T
A
= 0 to 70
°
C, –20 to 85
°
C or –40 to 85
°
C)
Toggle bit (DQ6).
When Programming operations
are in progress, successiveattempts to read DQ6
will output complementary data. DQ6 will toggle
following toggling of either G or E when G is low.
The operation is completed when two successive
reads yield the same output data. The next read
will output the bit last programmed or a ’1’ after
erasing. Thetogglebitis validonlyeffectiveduring
P/E.C. operations, that is after the fourth W pulse
for programming or after the sixth W pulse for
Erase. If the byte to be programmedbelongs to a
protectedblockthe commandwillbeignored.Ifthe
blocksselectedforerasureareprotected,DQ6will
toggle for about 100
μ
s and then return back to
Read. See Figure 11 for Toggle Bit flowchart and
Figure 12 for ToggleBit waveforms.
Error bit (DQ5).
This bit is set to ’1’ by the P/E.C
when there is a failure of byte programming, block
erase, or chip erase that results in invalid data
being programmedin thememoryblock.In caseof
error in block erase or byte program, the block in
which the error occured or to which the pro-
grammedbyte belongs,mustbe discarded. Other
blocksmaystillbeused.Errorbitresetsafter Reset
(RST) instruction. In case of success,the error bit
will set to ’0’ during Program or Erase and to valid
data afterwrite operation is completed.
Erase Timer bit (DQ3).
Thisbit is set to ’0’ by the
P/E.C. when the last Block Erase command has
been entered to the Command Interface and it is
awaiting the Erase start. When the erase timeout
period is finished, after 80 to 120
μ
s, DQ3 returns
back to ’1’.
Coded Cycles.
The two coded cycles unlock the
Command Interface.They are followed by a com-
mand input or a comand confirmation. The coded
cycles consist of writing the data AAh at address
5555hduringthefirstcycleanddata55hataddress
2AAAh during the second cycle. Addresses are
latched on the falling edge of W or E while data is
latched on the rising edge of W or E. The coded
cycles happen on first and second cycles of the
command write or on the fourth and fifth cycles.
10/31
M29W040
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