參數(shù)資料
型號(hào): M29W040-150K1R
廠商: 意法半導(dǎo)體
英文描述: Dual Low-Noise High-Speed Precision Operational Amplifier 8-SOIC
中文描述: 4兆位512KB的× 8,統(tǒng)一座低電壓單電源閃存
文件頁數(shù): 8/31頁
文件大小: 205K
代理商: M29W040-150K1R
Instructionsand Commands
The Command Interface (C.I.) latches commands
written to the memory. Instructions are made up
from one or more commands to perform Read
Array/Reset, Read Electronic Signature, Power
Down, Block Erase, Chip Erase, Program, Block
Erase Suspend and Erase Resume. Commands
are made of address and data sequences. Ad-
dresses are latchedon the falling edge of W or E
and data is latched on the rising of W or E. The
instructionsrequire from 1 to 6 cycles, the first or
first three of which are always write operations
used to initiatethecommand.Theyarefollowedby
either further write cyclesto confirmthe first com-
mand orexecutethe commandimmediately.Com-
mand sequencing must be followed exactly. Any
invalid combination of commands will reset the
device to Read Array. The increased number of
cycles has been chosen to assure maximum data
security.Commandsare initialised by two preced-
ingcodedcycleswhichunlocktheCommandInter-
face.In addition,for Erase,command confirmation
is againpreceededby the two codedcycles.
P/E.C. statusis indicatedduring command execu-
tionby DataPolling onDQ7,detectionofToggleon
DQ
Name
Logic Level
Definition
Note
7
Data
Polling
’1’
Erase Complete
Indicates the P/E.C. status, check during
Program or Erase, and on completion
before checking bits DQ5 for Program or
Erase Success.
’0’
Erase on going
DQ
Program Complete
DQ
Program on going
6
ToggleBit
’-1-0-1-0-1-0-1-’
Erase or Program ongoing
Successive read outputcomplementary
data on DQ6 whileProgramming or Erase
operations are going on. DQ6 remain at
constant level when P/E.C. operations are
completed or Erase Suspend is
acknowledged.
’-0-0-0-0-0-0-0-’
Program (’0’ on DQ6)
Complete
’-1-1-1-1-1-1-1-’
Erase or Program
(’1’ on DQ6) Complete
5
Error Bit
’1’
Program or Erase Error
This bit is set to ’1’if P/E.C. has exceded
the specified time limits.
’0’
Program or Erase on going
4
’1’
’0’
3
Erase
Time Bit
’1’
Erase TimeoutPeriod Expired
P/E.C. Erase operation has started. Only
possible command entry is Erase Suspend
(ES). An additional block to be erased in
parallel can be entered to the P/E.C.
’0’
Erase Timeout Period on
going
2
Reserved
1
Reserved
0
Reserved
Note:
Logic level ’1’ isHigh, ’0’ is Low.-0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.
Table8. StatusRegister
DQ6, or Error on DQ5 and Erase Timer DQ3 bits.
Any read attempt during Program or Erase com-
mandexecutionwillautomaticallyoutputthosefour
bits.TheP/E.C. automaticallysetsbitsDQ3,DQ5,
DQ6 and DQ7. Other bits (DQ0, DQ1, DQ2 and
DQ4) are reserved for future use and should be
masked.
Data Polling bit (DQ7).
When Programming op-
erations are in progress, this bit outputs the com-
plement of the bit being programmed on DQ7.
DuringErase operation,it outputsa ’0’. After com-
pletionof the operation,DQ7 willoutput thebit last
programmed or a ’1’ after erasing. Data Polling is
valid only effectiveduringP/E.C. operation,that is
after the fourth W pulse for programming or after
the sixth W pulse for Erase. It must be performed
at theaddressbeingprogrammedor at anaddress
within the block being erased. If the byte to be
programmedbelongsto aprotectedblockthecom-
mand is ignored. If all the blocks selected for era-
sure are protected, DQ7 will set to ’0’ for about
100
μ
s, and then return to previous addressed
memory data. See Figure 9 for the Data Polling
flowchart and Figure10 for the Data Polling wave-
forms.
8/31
M29W040
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