參數(shù)資料
型號: M29F400BT90M1F
廠商: 意法半導(dǎo)體
英文描述: 4 Mbit (512Kb x8 or 256Kb x16, Boot Block) single supply Flash memory
中文描述: 4兆位(512KB的x8或256Kb的x16插槽,引導(dǎo)塊)單電源閃存
文件頁數(shù): 13/40頁
文件大小: 215K
代理商: M29F400BT90M1F
M29F400BT, M29F400BB
Bus operations
13/40
3
Bus operations
There are five standard bus operations that control the device. These are Bus Read, Bus
Write, Output Disable, Standby and Automatic Standby. See
Table 2.
and
Table 3.
, Bus
Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write
Enable are ignored by the memory and do not affect bus operations.
3.1
Bus Read
Bus Read operations read from the memory cells, or specific registers in the Command
Interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs, applying a Low signal, V
IL
, to Chip Enable and Output Enable and keeping Write
Enable High, V
IH
. The Data Inputs/Outputs will output the value, see
Figure 8.
, Read Mode
AC Waveforms, and
Table 12.
, Read AC Characteristics, for details of when the output
becomes valid.
3.2
Bus Write
Bus Write operations write to the Command Interface. A valid Bus Write operation begins by
setting the desired address on the Address Inputs. The Address Inputs are latched by the
Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs
last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of
Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, V
IH
,
during the whole Bus Write operation. See
Figure 9.
and
Figure 10.
, Write AC Waveforms,
and
Table 13.
and
Table 14.
, Write AC Characteristics, for details of the timing requirements.
3.3
Output Disable
The Data Inputs/Outputs are in the high impedance state when Output Enable is High, V
IH
.
3.4
Standby
When Chip Enable is High, V
IH
, the Data Inputs/Outputs pins are placed in the high-
impedance state and the Supply Current is reduced to the Standby level.
When Chip Enable is at V
IH
the Supply Current is reduced to the TTL Standby Supply
Current, I
CC2
. To further reduce the Supply Current to the CMOS Standby Supply Current,
I
CC3
, Chip Enable should be held within V
CC
± 0.2V. For Standby current levels see
Table
11.
, DC Characteristics.
During program or erase operations the memory will continue to use the Program/Erase
Supply Current, I
CC4
, for Program or Erase operations until the operation completes.
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