參數(shù)資料
型號(hào): M28C16-120N1T
廠商: 意法半導(dǎo)體
元件分類: EEPROM
英文描述: 16K 2K x 8 PARALLEL EEPROM with SOFTWARE DATA PROTECTION
中文描述: 16K的2K × 8的并行EEPROM,帶有軟件數(shù)據(jù)保護(hù)
文件頁(yè)數(shù): 4/18頁(yè)
文件大?。?/td> 129K
代理商: M28C16-120N1T
Page Write
Page write allows up to 64 bytes to be consecu-
tively latched into the memory prior to initiating a
programming cycle.All bytes must be located in a
single page address, that is A6-A10 must be the
samefor all bytes. The page write can be initiated
during any byte write operation.
Following the first byte write instruction the host
may send another address and data with a mini-
mum datatransfer rateof 1/t
WHWH
(seeFigure13).
If atransitionofEorWisnotdetectedwithint
WHWH
,
the internalprogrammingcycle will start.
Chip Erase
The contentsof the entire memory may be erased
to FFh by use of the Chip Erase command by
setting Chip Enable (E) Low and Output Enable
(G) to V
CC
+7V. The chip is clearedwhen a 10ms
low pulse is applied to the WriteEnable pin.
Microcontroller Control Interface
The M28C16 provides two write operation status
bitsandonestatuspinthatcanbeusedtominimize
the system write cycle. Thesesignals areavailable
on the I/O port bits DQ7 or DQ6 of the memory
duringprogrammingcycle only.
Data Polling bit (DQ7).
During the internal write
cycle, any attempt to read thelast byte written will
produce on DQ7 the complementary value of the
previously latched bit. Once the write cycle is fin-
ished the true logic value appears on DQ7 in the
read cycle.
Toggle bit (DQ6).
The M28C16offersanotherway
for determining when the internal write cycle is
completed. During the internal Erase/Write cycle,
DQ6 will toggle from ”0” to ”1” and ”1” to ”0” (the
first read value is ”0”) on subsequent attempts to
read thememory. When the internalcycle is com-
pleted the toggling will stop and the device will be
accessible for a newRead or Write operation.
Page Load Timer Status bit (DQ5)
. In the Page
Write mode data may be latchedby E or W. Up to
64 bytes may be input. The Data output (DQ5)
indicates the status of the internal Page Load
Timer. DQ5 may be read by asserting Output En-
able Low (t
PLTS
). DQ5 Low indicates the timer is
running, High indicates time-out after which the
writecycle will start andno new data may be input.
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
DP
TB
PLTS Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Figure4. StatusBit Assignment
DP =Data Polling
TB = Toggle Bit
PLTS = Page Load Timer Status
AI01520
ADDRESS
LATCH
A6-A10
(Page Address)
X
CONTROL LOGIC
64K ARRAY
ADDRESS
LATCH
A0-A5
Y DECODE
VPPGEN
RESET
SENSE AND DATA LATCH
I/O BUFFERS
E
G
W
PAGE
LOAD
TIMER
STATUS
TOGGLE BIT
DATA POLLING
DQ0-DQ7
Figure3. Block Diagram
4/18
M28C16
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