參數(shù)資料
型號(hào): M27W401-100F6TR
廠商: 意法半導(dǎo)體
英文描述: 4 Mbit 512Kb x 8 Low Voltage UV EPROM and OTP EPROM
中文描述: 4兆位512KB的× 8低壓紫外線可擦寫可編程只讀存儲(chǔ)器和OTP存儲(chǔ)器
文件頁(yè)數(shù): 8/15頁(yè)
文件大小: 102K
代理商: M27W401-100F6TR
M27W401
8/15
Figure 7. Programming Flowchart
AI00760C
n = 0
Last
Addr
VERIFY
E = 100
μ
s Pulse
++n
= 25
++ Addr
VCC= 6.25V, VPP= 12.75V
FAIL
CHECK ALL BYTES
1st: VCC= 5V
2nd: VCC= 2.7V
YES
NO
YES
NO
YES
NO
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows the
whole array to be programmed with a guaranteed
margin, in a typical time of 52.5 seconds. Pro-
gramming with PRESTO II consists of applying a
sequence of 100
μ
s program pulses to each byte
until a correct verify occurs (see Figure 7). During
programming and verify operation, a MARGIN
MODE circuit is automatically activated in order to
guarantee that each cell is programmed with
enough margin. No overprogram pulse is applied
since the verify in MARGIN MODE at VCC much
higher than 3.6V, provides the necessary margin
to each programmed cell.
Program Inhibit
Programming of multiple M27W401s in parallel
with different data is also easily accomplished. Ex-
cept for E, all likeinputs including G of the parallel
M27W401 may be common. ATTL low level pulse
applied to a M27W401’s E input, with V
PP
at
12.75V, will program that M27W401. A high level
E input inhibits the other M27W401s from being
programmed.
Program Verify
A verify (read) should be performed on the pro-
grammed bits to determine that theywere correct-
ly programmed. The verify is accomplished with G
at V
IL
, E at V
IH
, V
PP
at 12.75V and V
CC
at 6.25V.
Figure 6. Programming and Verify Modes AC Waveforms
tAVPL
VALID
AI00725
A0-A18
Q0-Q7
VPP
VCC
G
DATA IN
DATA OUT
E
tQVEL
tVPHEL
tVCHEL
tEHQX
tELEH
tGLQV
tQXGL
tGHQZ
tGHAX
PROGRAM
VERIFY
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