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參數(shù)資料
| 型號(hào)： | M27V512-200F1TR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Quadruple 2-Input Positive-NAND Buffers/Drivers 14-PDIP 0 to 70 |
| 中文描述： | 512千位64Kb的x8低壓紫外線EPROM和檢察官辦公室存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 9/16頁(yè) |
| 文件大?。?/td> | 108K |
| 代理商： | M27V512-200F1TR |
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M27V512
PRESTO IIB Programming Algorithm
PRESTO IIB Programming Algorithm allows the
whole array to be programmed with a guaranteed
margin, in a typical time of 6.5 seconds. This can
be achieved with STMicroelectronics M27V512
due to several design innovations described in the
M27V512 datasheet to improve programming effi-
ciency and to provide adequate marginfor reliabil-
ity. Before starting the programming the internal
MARGIN MODE circuit is set in order to guarantee
that each cell is programmed with enough margin.
Then a sequence of100
μ
s program pulses are ap-
plied to each byte until a correct verify occurs. No
overprogram pulses are applied since the verify in
MARGIN MODE provides the necessary margin.
Program Inhibit
Programming of multiple M27V512s in parallel
with different data is also easily accomplished. Ex-
cept for E, alllike inputs including GV
PP
of thepar-
allel M27V512 may be common. A TTL low level
pulse applied to a M27V512’s E input, with V
PP
at
12.75V, will program that M27V512. A high level E
input inhibits the other M27V512s from being pro-
grammed.
Program Verify
A verify (read) should be performed on the pro-
grammed bits to determine that theywere correct-
ly programmed. The verify is accomplished with G
at V
IL
. Data should be verified with t
ELQV
after the
falling edge of E.
Figure 7. Programming and Verify Modes AC Waveforms
AI00737
tVPLEL
PROGRAM
DATA IN
A0-A15
E
GVPP
Q0-Q7
DATA OUT
tAVEL
tQVEL
tVCHEL
tVPHEL
tEHQX
tEHVPX
tELEH
tELQV
tEHAX
tEHQZ
VERIFY
VALID
VCC
Figure 8. Programming Flowchart
AI00738B
n = 0
Last
Addr
VERIFY
E = 100
μ
s Pulse
++n
= 25
++ Addr
VCC= 6.25V, VPP= 12.75V
FAIL
CHECK ALL BYTES
1st: VCC= 6V
2nd: VCC= 4.2V
YES
NO
YES
NO
YES
NO
SET MARGIN MODE
RESET MARGINMODE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M27V512-200B6TR | 512 Kbit 64Kb x8 Low Voltage UV EPROM and OTP EPROM |
| M27V512-200B1TR | 512 Kbit 64Kb x8 Low Voltage UV EPROM and OTP EPROM |
| M27V512-150N6TR | 512 Kbit 64Kb x8 Low Voltage UV EPROM and OTP EPROM |
| M27V512-150N1TR | 512 Kbit 64Kb x8 Low Voltage UV EPROM and OTP EPROM |
| M27V512-150K6TR | 512 Kbit 64Kb x8 Low Voltage UV EPROM and OTP EPROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M27V512-200F6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:512 Kbit 64Kb x8 Low Voltage UV EPROM and OTP EPROM |
| M27V512-200K1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:512 Kbit 64Kb x8 Low Voltage UV EPROM and OTP EPROM |
| M27V512-200K6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:512 Kbit 64Kb x8 Low Voltage UV EPROM and OTP EPROM |
| M27V512-200N1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:512 Kbit 64Kb x8 Low Voltage UV EPROM and OTP EPROM |
| M27V512-200N6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:512 Kbit 64Kb x8 Low Voltage UV EPROM and OTP EPROM |
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