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參數資料
| 型號： | M27C202-70N6TR |
| 廠商： | 意法半導體 |
| 英文描述： | 2 Mbit 128Kb x16 UV EPROM and OTP EPROM |
| 中文描述： | 2兆位存儲器128KB的x16紫外線和OTP存儲器 |
| 文件頁數： | 8/15頁 |
| 文件大?。?/td> | 102K |
| 代理商： | M27C202-70N6TR |
M27C202
8/15
Figure 6. Programming and Verify Modes AC Waveforms
tAVPL
VALID
AI00706
A0-A15
Q0-Q15
VPP
VCC
P
G
DATA IN
DATA OUT
E
tQVPL
tVPHPL
tVCHPL
tPHQX
tPLPH
tGLQV
tQXGL
tELPL
tGHQZ
tGHAX
PROGRAM
VERIFY
Figure 7. Programming Flowchart
AI00707C
n = 0
Last
Addr
VERIFY
P = 100
μ
s Pulse
++n
= 25
++ Addr
VCC= 6.25V, VPP= 12.75V
FAIL
CHECK ALL WORDS
1st: VCC= 6V
2nd: VCC= 4.2V
YES
NO
YES
NO
YES
NO
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows pro-
gramming of the whole array with a guaranteed
margin, in a typical time of 13 seconds. Program-
ming with PRESTO II consists of applying a se-
quence of 100
μ
s program pulses to each word
until a correct verify occurs (see Figure 7). During
programming and verify operation, a MARGIN
MODE circuit is automatically activated in order to
guarantee that each cell is programmed with
enough margin. No overprogram pulse is applied
since the verify in MARGIN MODE provides nec-
essary margin to each programmed cell.
Program Inhibit
Programming of multiple M27C202s in parallel
with different data is also easily accomplished. Ex-
cept for E, all likeinputs including G of the parallel
M27C202 may be common. A TTL low level pulse
applied to a M27C202’s P input, with E low and
V
PP
at 12.75V, will program that M27C202. A high
level E input inhibits the other M27C202s from be-
ing programmed.
Program Verify
A verify (read) should be performed on the pro-
grammed bits to determine that theywere correct-
ly programmed. The verify is accomplished with E
and G at V
IL
, P at V
IH
, V
PP
at 12.75V and V
CC
at
6.25V.
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