參數資料
型號： M27C202-70N6TR
廠商： 意法半導體
英文描述： 2 Mbit 128Kb x16 UV EPROM and OTP EPROM
中文描述： 2兆位存儲器128KB的x16紫外線和OTP存儲器
文件頁數： 5/15頁
文件大?。?/td> 102K
代理商： M27C202-70N6TR
5/15
M27C202
Table 7. Read Mode DC Characteristics
(1)
(T
A
= 0 to 70
°
C, –40 to 85
°
C or –40 to 125
°
C; V
CC
= 5V
±
10%; V
PP
= V
CC
)
Symbol
Parameter
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Maximum DC voltage on Output is V
CC
+0.5V.
Test Condition
Min
Max
Unit
I
LI
Input Leakage Current
0V
≤
V
IN
≤
V
CC
±
10
μ
A
I
LO
Output Leakage Current
0V
≤
V
OUT
≤
V
CC
±
10
μ
A
I
CC
Supply Current
E = V
IL
, G = V
IL
,
I
OUT
= 0mA, f = 5MHz
50
mA
I
CC1
Supply Current (Standby) TTL
E = V
IH
1
mA
I
CC2
Supply Current (Standby) CMOS
E > V
CC
– 0.2V
100
μ
A
I
PP
Program Current
V
PP
= V
CC
100
μ
A
V
IL
Input Low Voltage
–0.3
0.8
V
V
IH(2)
Input High Voltage
2
V
CC
+ 1
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
V
OH
Output High Voltage TTL
I
OH
= –400
μ
A
2.4
V
Output High Voltage CMOS
I
OH
= –100
μ
A
V
CC
– 0.7V
V
Two Line Output Control
Because OTP EPROMs are usually used in larger
memory arrays, this product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, Eshould be decodedand used as theprima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system controlbus. This ensures that all deselect-
ed memory devices are intheir low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, I
CC
, has three seg-
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the fallingand rising edges of E. The magnitude of
transient current peaks is dependent on the ca-
pacitive and inductive loading of the device at the
output. The associated transient voltage peaks
can be suppressed by complying with the two line
output control and by properly selected decoupling
capacitors. It is recommended that a 0.1
μ
F ceram-
ic capacitorbe used on every device between V
CC
and V
SS
. This should be a high frequency capaci-
tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
tion, a 4.7
μ
F bulk electrolytic capacitor should be
used between V
CC
and V
SS
for every eight devic-
es. The bulk capacitor should be located near the
power supply connection point.Thepurpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
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相關代理商/技術參數
參數描述
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